+ /* Note: although the value is still live here, it is destroyed because
+ of the pop. The register allocator is aware of that and introduced a copy
+ if the value must be alive. */
+
+ /* we can only store the tos to memory */
+ if (op2_idx != 0)
+ x87_create_fxch(state, n, op2_idx);
+
+ x87_pop(state);
+ x87_patch_insn(n, op_ia32_fisttp);
+
+ attr = get_ia32_x87_attr(n);
+ attr->x87[1] = op2 = &ia32_st_regs[0];
+ DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
+
+ return NO_NODE_ADDED;
+} /* sim_fisttp */
+
+/**
+ * Simulate a virtual FtstFnstsw.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
+static int sim_FtstFnstsw(x87_state *state, ir_node *n)
+{
+ x87_simulator *sim = state->sim;
+ ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
+ ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
+ const arch_register_t *reg1 = x87_get_irn_register(op1_node);
+ int reg_index_1 = arch_register_get_index(reg1);
+ int op1_idx = x87_on_stack(state, reg_index_1);
+ unsigned live = vfp_live_args_after(sim, n, 0);
+
+ DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
+ DEBUG_ONLY(vfp_dump_live(live));
+ DB((dbg, LEVEL_1, "Stack before: "));
+ DEBUG_ONLY(x87_dump_stack(state));
+ assert(op1_idx >= 0);
+
+ if (op1_idx != 0) {
+ /* bring the value to tos */
+ x87_create_fxch(state, n, op1_idx);
+ op1_idx = 0;
+ }
+
+ /* patch the operation */
+ x87_patch_insn(n, op_ia32_FtstFnstsw);
+ reg1 = &ia32_st_regs[op1_idx];
+ attr->x87[0] = reg1;
+ attr->x87[1] = NULL;
+ attr->x87[2] = NULL;
+
+ if (!is_vfp_live(reg_index_1, live))
+ x87_create_fpop(state, sched_next(n), 1);
+
+ return NO_NODE_ADDED;
+} /* sim_FtstFnstsw */
+
+/**
+ * Simulate a Fucom
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
+static int sim_Fucom(x87_state *state, ir_node *n)
+{
+ int op1_idx;
+ int op2_idx = -1;
+ ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
+ ir_op *dst;
+ x87_simulator *sim = state->sim;
+ ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
+ ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
+ const arch_register_t *op1 = x87_get_irn_register(op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(op2_node);
+ int reg_index_1 = arch_register_get_index(op1);
+ int reg_index_2 = arch_register_get_index(op2);
+ unsigned live = vfp_live_args_after(sim, n, 0);
+ int permuted = attr->attr.data.ins_permuted;
+ int xchg = 0;
+ int pops = 0;
+
+ DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
+ arch_register_get_name(op1), arch_register_get_name(op2)));
+ DEBUG_ONLY(vfp_dump_live(live));
+ DB((dbg, LEVEL_1, "Stack before: "));
+ DEBUG_ONLY(x87_dump_stack(state));
+
+ op1_idx = x87_on_stack(state, reg_index_1);
+ assert(op1_idx >= 0);