+GEN_LOAD(fld)
+GEN_LOAD(fild)
+GEN_LOAD(fldz)
+GEN_LOAD(fld1)
+GEN_LOAD2(fConst, fldConst)
+
+GEN_STORE(fst)
+GEN_STORE(fist)
+
+/**
+ * Simulate a fCondJmp.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ * @param env the architecture environment
+ */
+static void sim_fCondJmp(x87_state *state, ir_node *n, const arch_env_t *env) {
+ int op2_idx, op1_idx = -1, pop_cnt = 0;
+ ia32_attr_t *attr;
+ ir_op *dst;
+ const arch_register_t *op1 = arch_get_irn_register(env, get_irn_n(n, BINOP_IDX_1));
+ const arch_register_t *op2 = arch_get_irn_register(env, get_irn_n(n, BINOP_IDX_2));
+ unsigned live = vfp_liveness_nodes_live_at(env, n);
+
+ DB((dbg, LEVEL_1, ">>> %s %s, %s\n", get_irn_opname(n),
+ arch_register_get_name(op1), arch_register_get_name(op2)));
+ DEBUG_ONLY(vfp_dump_live(live));
+
+ op1_idx = x87_on_stack(state, arch_register_get_index(op1));
+ op2_idx = x87_on_stack(state, arch_register_get_index(op2));
+
+ /* BEWARE: check for comp a,a cases, they might happen */
+ if (op2->index != REG_VFP_NOREG) {
+ /* second operand is a vfp register */
+
+ if (is_vfp_live(op2->index, live)) {
+ /* second operand is live */
+
+ if (is_vfp_live(op1->index, live)) {
+ /* both operands are live: move one of them to tos */
+ if (op2_idx == 0) {
+ XCHG(op2_idx, op1_idx);
+ dst = op_ia32_fcomrJmp;
+ }
+ else if (op1_idx == 0) {
+ dst = op_ia32_fcomJmp;
+ }
+ else {
+ /* bring the first on top */
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ if (op1_idx == op2_idx)
+ op2_idx = 0;
+ op1_idx = 0;
+ dst = op_ia32_fcomJmp;
+ }
+ }
+ else {
+ /* second live, first operand is dead here, bring it to tos.
+ This means further, op1_idx != op2_idx. */
+ if (op1_idx != 0) {
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ if (op2_idx == 0)
+ op2_idx = op1_idx;
+ }
+ op1_idx = 0;
+ dst = op_ia32_fcompJmp;
+ pop_cnt = 1;
+ }
+ }
+ else {
+ /* second operand is dead */
+ if (is_vfp_live(op1->index, live)) {
+ /* first operand is live: bring second to tos.
+ This means further, op1_idx != op2_idx. */
+ if (op2_idx != 0) {
+ x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ if (op1_idx == 0)
+ op1_idx = op2_idx;
+ }
+ op2_idx = 0;
+ dst = op_ia32_fcomrpJmp;
+ pop_cnt = 1;
+ }
+ else {
+ /* both operands are dead here, check first for identity. */
+ if (op1_idx == op2_idx) {
+ /* identically, one one needed */
+ if (op1_idx != 0) {
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ op1_idx = op2_idx = 0;
+ }
+ dst = op_ia32_fcompJmp;
+ pop_cnt = 1;
+ }
+ /* different, move them to st and st(1) and pop both.
+ The tricky part is to get one into st(1).*/
+ else if (op2_idx == 1) {
+ /* good, second operand is already in the right place, move the first */
+ if (op1_idx != 0) {
+ /* bring the first on top */
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ op1_idx = 0;
+ }
+ dst = op_ia32_fcomppJmp;
+ pop_cnt = 2;
+ }
+ else if (op1_idx == 1) {
+ /* good, first operand is already in the right place, move the second */
+ if (op2_idx != 0) {
+ /* bring the first on top */
+ x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ op2_idx = 0;
+ }
+ dst = op_ia32_fcomrppJmp;
+ pop_cnt = 2;
+ }
+ else {
+ /* if one is already the TOS, we need two fxch */
+ if (op1_idx == 0) {
+ /* first one is TOS, move to st(1) */
+ x87_create_fxch(state, n, 1, BINOP_IDX_1);
+ op1_idx = 1;
+ x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ op2_idx = 0;
+ dst = op_ia32_fcomrppJmp;
+ pop_cnt = 2;
+ }
+ else if (op2_idx == 0) {
+ /* second one is TOS, move to st(1) */
+ x87_create_fxch(state, n, 1, BINOP_IDX_2);
+ op2_idx = 1;
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ op1_idx = 0;
+ dst = op_ia32_fcomrppJmp;
+ pop_cnt = 2;
+ }
+ else {
+ /* none of them is either TOS or st(1), 3 fxch needed */
+ x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, 1, BINOP_IDX_2);
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ op1_idx = 0;
+ op2_idx = 1;
+ dst = op_ia32_fcomppJmp;
+ pop_cnt = 2;
+ }
+ }
+ }
+ }
+ }
+ else {
+ /* second operand is an address mode */
+ if (is_vfp_live(op1->index, live)) {
+ /* first operand is live: bring it to TOS */
+ if (op1_idx != 0) {
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ op1_idx = 0;
+ }
+ dst = op_ia32_fcomJmp;
+ }
+ else {
+ /* first operand is dead: bring it to tos */
+ if (op1_idx != 0) {
+ x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ op1_idx = 0;
+ }
+ }
+ dst = op_ia32_fcompJmp;
+ pop_cnt = 1;
+ }
+
+ x87_patch_insn(n, dst);
+ if (pop_cnt > 1)
+ x87_pop(state);
+ if (pop_cnt > 0)
+ x87_pop(state);
+
+ /* patch the operation */
+ attr = get_ia32_attr(n);
+ attr->x87[0] = op1 = &ia32_st_regs[op1_idx];
+ if (op2_idx >= 0)
+ attr->x87[1] = op2 = &ia32_st_regs[op2_idx];
+
+ if (op2_idx >= 0)
+ DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
+ arch_register_get_name(op1), arch_register_get_name(op2)));
+ else
+ DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
+ arch_register_get_name(op1)));
+}
+