struct _x87_simulator {
struct obstack obst; /**< An obstack for fast allocating. */
pmap *blk_states; /**< Map blocks to states. */
struct _x87_simulator {
struct obstack obst; /**< An obstack for fast allocating. */
pmap *blk_states; /**< Map blocks to states. */
be_lv_t *lv; /**< intrablock liveness. */
vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
be_lv_t *lv; /**< intrablock liveness. */
vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
* @param node the IR node that produces the value of the vfp register
* @param pos the stack position where the new value should be entered
*/
* @param node the IR node that produces the value of the vfp register
* @param pos the stack position where the new value should be entered
*/
-static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
+static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
+{
assert(0 < state->depth);
state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
state->st[MASK_TOS(state->tos + pos)].node = node;
assert(0 < state->depth);
state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
state->st[MASK_TOS(state->tos + pos)].node = node;
* @param reg_idx the vfp register index that should be set
* @param node the IR node that produces the value of the vfp register
*/
* @param reg_idx the vfp register index that should be set
* @param node the IR node that produces the value of the vfp register
*/
x87_set_st(state, reg_idx, node, 0);
} /* x87_set_tos */
x87_set_st(state, reg_idx, node, 0);
} /* x87_set_tos */
* @return the stack position where the register is stacked
* or -1 if the virtual register was not found
*/
* @return the stack position where the register is stacked
* or -1 if the virtual register was not found
*/
* @param reg_idx the register vfp index
* @param node the node that produces the value of the vfp register
*/
* @param reg_idx the register vfp index
* @param node the node that produces the value of the vfp register
*/
* @param node the node that produces the value of the vfp register
* @param dbl_push if != 0 double pushes are allowed
*/
* @param node the node that produces the value of the vfp register
* @param dbl_push if != 0 double pushes are allowed
*/
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
x87_push_dbl(state, reg_idx, node);
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
x87_push_dbl(state, reg_idx, node);
x87_state *res = x87_alloc_state(sim);
memcpy(res, src, sizeof(*res));
x87_state *res = x87_alloc_state(sim);
memcpy(res, src, sizeof(*res));
-static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
- const arch_register_t *res;
+static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
+{
+ const arch_register_t *res = arch_get_irn_register(irn);
-static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
+static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
+{
* Updates a live set over a single step from a given node to its predecessor.
* Everything defined at the node is removed from the set, the uses of the node get inserted.
*
* Updates a live set over a single step from a given node to its predecessor.
* Everything defined at the node is removed from the set, the uses of the node get inserted.
*
* @param irn The node at which liveness should be computed.
* @param live The bitset of registers live before @p irn. This set gets modified by updating it to
* the registers live after irn.
*
* @return The live bitset.
*/
* @param irn The node at which liveness should be computed.
* @param live The bitset of registers live before @p irn. This set gets modified by updating it to
* the registers live after irn.
*
* @return The live bitset.
*/
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
- if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
- const arch_register_t *reg = x87_get_irn_register(sim, proj);
+ if (arch_irn_consider_in_reg_alloc(cls, proj)) {
+ const arch_register_t *reg = x87_get_irn_register(proj);
- if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
- const arch_register_t *reg = x87_get_irn_register(sim, irn);
+ if (arch_irn_consider_in_reg_alloc(cls, irn)) {
+ const arch_register_t *reg = x87_get_irn_register(irn);
live &= ~(1 << arch_register_get_index(reg));
}
for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
ir_node *op = get_irn_n(irn, i);
live &= ~(1 << arch_register_get_index(reg));
}
for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
ir_node *op = get_irn_n(irn, i);
- if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
- const arch_register_t *reg = x87_get_irn_register(sim, op);
+ if (mode_is_float(get_irn_mode(op)) &&
+ arch_irn_consider_in_reg_alloc(cls, op)) {
+ const arch_register_t *reg = x87_get_irn_register(op);
const be_lv_t *lv = sim->lv;
be_lv_foreach(lv, block, be_lv_state_end, i) {
const arch_register_t *reg;
const ir_node *node = be_lv_get_irn(lv, block, i);
const be_lv_t *lv = sim->lv;
be_lv_foreach(lv, block, be_lv_state_end, i) {
const arch_register_t *reg;
const ir_node *node = be_lv_get_irn(lv, block, i);
ir_node *patched_insn;
ir_op *dst;
x87_simulator *sim = state->sim;
ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
ir_node *patched_insn;
ir_op *dst;
x87_simulator *sim = state->sim;
ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
- const arch_register_t *op1_reg = x87_get_irn_register(sim, op1);
- const arch_register_t *op2_reg = x87_get_irn_register(sim, op2);
- const arch_register_t *out = x87_get_irn_register(sim, n);
+ const arch_register_t *op1_reg = x87_get_irn_register(op1);
+ const arch_register_t *op2_reg = x87_get_irn_register(op2);
+ const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state));
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state));
/* first operand is live: push it here */
x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
op1_idx = 0;
/* first operand is live: push it here */
x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
op1_idx = 0;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
if (reg_index_2 != REG_VFP_NOREG) {
attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
if (reg_index_2 != REG_VFP_NOREG) {
attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
- const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
- const arch_register_t *out = x87_get_irn_register(sim, n);
+ const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, UNOP_IDX));
+ const arch_register_t *out = x87_get_irn_register(n);
-static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
- const arch_register_t *out = x87_get_irn_register(state->sim, n);
+static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
+{
+ const arch_register_t *out = x87_irn_get_register(n, res_pos);
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
const ir_edge_t *edge, *ne;
foreach_out_edge_safe(old_val, edge, ne) {
const ir_edge_t *edge, *ne;
foreach_out_edge_safe(old_val, edge, ne) {
-static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
- x87_simulator *sim = state->sim;
+static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
+{
- const arch_register_t *op2 = x87_get_irn_register(sim, val);
- unsigned live = vfp_live_args_after(sim, n, 0);
+ const arch_register_t *op2 = x87_get_irn_register(val);
+ unsigned live = vfp_live_args_after(state->sim, n, 0);
int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
op2_reg_idx = arch_register_get_index(op2);
if (op2_reg_idx == REG_VFP_UKNWN) {
/* just take any value from stack */
op2_reg_idx = arch_register_get_index(op2);
if (op2_reg_idx == REG_VFP_UKNWN) {
/* just take any value from stack */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
if (is_ia32_use_frame(n))
set_ia32_use_frame(vfld);
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
if (is_ia32_use_frame(n))
set_ia32_use_frame(vfld);
add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
/* reroute all former users of the store memory to the load memory */
edges_reroute(mem, mproj, irg);
/* reroute all former users of the store memory to the load memory */
edges_reroute(mem, mproj, irg);
#define GEN_BINOP(op) _GEN_BINOP(op, op)
#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
#define GEN_BINOP(op) _GEN_BINOP(op, op)
#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
-#define GEN_LOAD2(op, nop) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_load(state, n, op_ia32_##nop); \
+#define GEN_LOAD(op) \
+static int sim_##op(x87_state *state, ir_node *n) { \
+ return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
#define GEN_UNOP(op) \
static int sim_##op(x87_state *state, ir_node *n) { \
return sim_unop(state, n, op_ia32_##op); \
#define GEN_UNOP(op) \
static int sim_##op(x87_state *state, ir_node *n) { \
return sim_unop(state, n, op_ia32_##op); \
int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
x87_simulator *sim = state->sim;
ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
x87_simulator *sim = state->sim;
ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
int reg_index_1 = arch_register_get_index(reg1);
int op1_idx = x87_on_stack(state, reg_index_1);
unsigned live = vfp_live_args_after(sim, n, 0);
int reg_index_1 = arch_register_get_index(reg1);
int op1_idx = x87_on_stack(state, reg_index_1);
unsigned live = vfp_live_args_after(sim, n, 0);
x87_simulator *sim = state->sim;
ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
x87_simulator *sim = state->sim;
ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
- const arch_register_t *op1 = x87_get_irn_register(sim, op1_node);
- const arch_register_t *op2 = x87_get_irn_register(sim, op2_node);
+ const arch_register_t *op1 = x87_get_irn_register(op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(op2_node);
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
unsigned live = vfp_live_args_after(sim, n, 0);
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
unsigned live = vfp_live_args_after(sim, n, 0);
DB((dbg, LEVEL_1, ">>> %+F\n", node));
arity = get_irn_arity(node);
DB((dbg, LEVEL_1, ">>> %+F\n", node));
arity = get_irn_arity(node);
- op_reg = arch_get_irn_register(state->sim->arch_env, op);
- if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
+ op_reg = arch_get_irn_register(op);
+ if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
continue;
reg_id = arch_register_get_index(op_reg);
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
continue;
reg_id = arch_register_get_index(op_reg);
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
in[0] = node;
keep = be_new_Keep(cls, irg, block, 1, in);
in[0] = node;
keep = be_new_Keep(cls, irg, block, 1, in);
ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
ir_mode *mode = get_irn_mode(n);
ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
ir_mode *mode = get_irn_mode(n);
- out = x87_get_irn_register(sim, n);
- op1 = x87_get_irn_register(sim, pred);
+ out = x87_get_irn_register(n);
+ op1 = x87_get_irn_register(pred);
- out = x87_get_irn_register(sim, n);
- op1 = x87_get_irn_register(sim, pred);
- live = vfp_live_args_after(sim, n, REGMASK(out));
+ out = x87_get_irn_register(n);
+ op1 = x87_get_irn_register(pred);
+ live = vfp_live_args_after(state->sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
arch_register_get_name(op1), arch_register_get_name(out)));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
arch_register_get_name(op1), arch_register_get_name(out)));
sched_add_before(next, node);
DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
sched_add_before(next, node);
DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
- if(get_irn_n_edges(pred) == 0) {
- keep_float_node_alive(state, pred);
+ if (get_irn_n_edges(pred) == 0) {
+ keep_float_node_alive(pred);
}
DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
}
DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
-static int sim_Spill(x87_state *state, ir_node *n) {
- assert(0 && "Spill not lowered");
+static int sim_Spill(x87_state *state, ir_node *n)
+{
+ panic("Spill not lowered");
-static int sim_Reload(x87_state *state, ir_node *n) {
- assert(0 && "Reload not lowered");
+static int sim_Reload(x87_state *state, ir_node *n)
+{
+ panic("Reload not lowered");
for (i = 0; i < n_res; ++i) {
ir_node *res = get_irn_n(n, be_pos_Return_val + i);
for (i = 0; i < n_res; ++i) {
ir_node *res = get_irn_n(n, be_pos_Return_val + i);
int idx = x87_on_stack(state, arch_register_get_index(inreg));
assert(idx >= 0 && "Perm argument not on x87 stack");
int idx = x87_on_stack(state, arch_register_get_index(inreg));
assert(idx >= 0 && "Perm argument not on x87 stack");
/* now do the permutation */
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
/* now do the permutation */
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
const arch_register_t *reg;
ir_node *zero;
ir_node *block;
ia32_x87_attr_t *attr;
ir_node *in = get_irn_n(node, i);
const arch_register_t *reg;
ir_node *zero;
ir_node *block;
ia32_x87_attr_t *attr;
ir_node *in = get_irn_n(node, i);
/* create a zero at end of pred block */
zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
/* create a zero at end of pred block */
zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
ir_node *n, *next;
blk_state *bl_state = x87_get_bl_state(sim, block);
x87_state *state = bl_state->begin;
ir_node *n, *next;
blk_state *bl_state = x87_get_bl_state(sim, block);
x87_state *state = bl_state->begin;
*
* @param sim a simulator handle, will be initialized
* @param irg the current graph
*
* @param sim a simulator handle, will be initialized
* @param irg the current graph
-static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
- const arch_env_t *arch_env)
+static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
sim->n_idx = get_irg_last_idx(irg);
sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
sim->n_idx = get_irg_last_idx(irg);
sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
/* set the generic function pointer of instruction we must simulate */
clear_irp_opcodes_generic_func();
/* set the generic function pointer of instruction we must simulate */
clear_irp_opcodes_generic_func();
register_sim(op_ia32_vfld, sim_fld);
register_sim(op_ia32_vfild, sim_fild);
register_sim(op_ia32_vfld1, sim_fld1);
register_sim(op_ia32_vfld, sim_fld);
register_sim(op_ia32_vfild, sim_fild);
register_sim(op_ia32_vfld1, sim_fld1);
register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
register_sim(op_ia32_vFucomi, sim_Fucom);
register_sim(op_be_Copy, sim_Copy);
register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
register_sim(op_ia32_vFucomi, sim_Fucom);
register_sim(op_be_Copy, sim_Copy);
register_sim(op_be_Spill, sim_Spill);
register_sim(op_be_Reload, sim_Reload);
register_sim(op_be_Return, sim_Return);
register_sim(op_be_Spill, sim_Spill);
register_sim(op_be_Reload, sim_Reload);
register_sim(op_be_Return, sim_Return);
pmap_destroy(sim->blk_states);
obstack_free(&sim->obst, NULL);
DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
pmap_destroy(sim->blk_states);
obstack_free(&sim->obst, NULL);
DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
* Pre-block walker: calculate the liveness information for the block
* and store it into the sim->live cache.
*/
* Pre-block walker: calculate the liveness information for the block
* and store it into the sim->live cache.
*/
x87_simulator *sim = data;
update_liveness(sim, block);
} /* update_liveness_walker */
x87_simulator *sim = data;
update_liveness(sim, block);
} /* update_liveness_walker */
-/**
- * Run a simulation and fix all virtual instructions for a graph.
- *
- * @param env the architecture environment
- * @param irg the current graph
- *
- * Needs a block-schedule.
- */
-void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
+void x87_simulate_graph(be_irg_t *birg)
+{
+ /* TODO improve code quality (less executed fxch) by using execfreqs */
+
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
ir_graph *irg = be_get_birg_irg(birg);
/* create the simulator */
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
ir_graph *irg = be_get_birg_irg(birg);
/* create the simulator */
start_block = get_irg_start_block(irg);
bl_state = x87_get_bl_state(&sim, start_block);
start_block = get_irg_start_block(irg);
bl_state = x87_get_bl_state(&sim, start_block);