+/**
+ * Transform the Projs of an AddSP.
+ */
+static ir_node *gen_Proj_be_AddSP(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ if (proj == pn_be_AddSP_res) {
+ ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
+ arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
+ return res;
+ } else if (proj == pn_be_AddSP_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+/**
+ * Transform the Projs of a SubSP.
+ */
+static ir_node *gen_Proj_be_SubSP(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ if (proj == pn_be_SubSP_res) {
+ ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
+ arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
+ return res;
+ } else if (proj == pn_be_SubSP_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+/**
+ * Transform and renumber the Projs from a Load.
+ */
+static ir_node *gen_Proj_Load(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ /* renumber the proj */
+ if (is_ia32_Load(new_pred)) {
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
+ }
+ } else if (is_ia32_xLoad(new_pred)) {
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
+ }
+ } else if (is_ia32_vfld(new_pred)) {
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
+ }
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+/**
+ * Transform and renumber the Projs from a DivMod like instruction.
+ */
+static ir_node *gen_Proj_DivMod(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
+
+ switch (get_irn_opcode(pred)) {
+ case iro_Div:
+ switch (proj) {
+ case pn_Div_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
+ case pn_Div_res:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
+ default:
+ break;
+ }
+ break;
+ case iro_Mod:
+ switch (proj) {
+ case pn_Mod_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
+ case pn_Mod_res:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
+ default:
+ break;
+ }
+ break;
+ case iro_DivMod:
+ switch (proj) {
+ case pn_DivMod_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
+ case pn_DivMod_res_div:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
+ case pn_DivMod_res_mod:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, mode);
+}
+
+/**
+ * Transform and renumber the Projs from a CopyB.
+ */
+static ir_node *gen_Proj_CopyB(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch(proj) {
+ case pn_CopyB_M_regular:
+ if (is_ia32_CopyB_i(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
+ } else if (is_ia32_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
+ }
+ break;
+ default:
+ break;
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, mode);
+}
+
+/**
+ * Transform and renumber the Projs from a vfdiv.
+ */
+static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch (proj) {
+ case pn_ia32_l_vfdiv_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
+ case pn_ia32_l_vfdiv_res:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ default:
+ assert(0);
+ }
+
+ return new_rd_Unknown(irg, mode);
+}
+
+/**
+ * Transform and renumber the Projs from a Quot.
+ */
+static ir_node *gen_Proj_Quot(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch(proj) {
+ case pn_Quot_M:
+ if (is_ia32_xDiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
+ } else if (is_ia32_vfdiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
+ }
+ break;
+ case pn_Quot_res:
+ if (is_ia32_xDiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
+ } else if (is_ia32_vfdiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ }
+ break;
+ default:
+ break;
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, mode);
+}
+
+/**
+ * Transform the Thread Local Storage Proj.
+ */
+static ir_node *gen_Proj_tls(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = NULL;
+ ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
+
+ return res;
+}
+
+/**
+ * Transform the Projs from a be_Call.
+ */
+static ir_node *gen_Proj_be_Call(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *call = get_Proj_pred(node);
+ ir_node *new_call = be_transform_node(call);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *sse_load;
+ const arch_register_class_t *cls;
+
+ /* The following is kinda tricky: If we're using SSE, then we have to
+ * move the result value of the call in floating point registers to an
+ * xmm register, we therefore construct a GetST0 -> xLoad sequence
+ * after the call, we have to make sure to correctly make the
+ * MemProj and the result Proj use these 2 nodes
+ */
+ if (proj == pn_be_Call_M_regular) {
+ // get new node for result, are we doing the sse load/store hack?
+ ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
+ ir_node *call_res_new;
+ ir_node *call_res_pred = NULL;
+
+ if (call_res != NULL) {
+ call_res_new = be_transform_node(call_res);
+ call_res_pred = get_Proj_pred(call_res_new);
+ }
+
+ if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
+ } else {
+ assert(is_ia32_xLoad(call_res_pred));
+ return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
+ }
+ }
+ if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
+ ir_node *fstp;
+ ir_node *frame = get_irg_frame(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *p;
+ ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
+ ir_node *keepin[1];
+ const arch_register_class_t *cls;
+
+ /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
+ call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
+
+ /* store st(0) onto stack */
+ fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
+
+ set_ia32_ls_mode(fstp, mode);
+ set_ia32_op_type(fstp, ia32_AddrModeD);
+ set_ia32_use_frame(fstp);
+ set_ia32_am_flavour(fstp, ia32_am_B);
+
+ /* load into SSE register */
+ sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
+ set_ia32_ls_mode(sse_load, mode);
+ set_ia32_op_type(sse_load, ia32_AddrModeS);
+ set_ia32_use_frame(sse_load);
+ set_ia32_am_flavour(sse_load, ia32_am_B);
+
+ sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
+
+ /* now: create new Keep whith all former ins and one additional in - the result Proj */
+
+ /* get a Proj representing a caller save register */
+ p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
+ assert(is_Proj(p) && "Proj expected.");
+
+ /* user of the the proj is the Keep */
+ p = get_edge_src_irn(get_irn_out_edge_first(p));
+ assert(be_is_Keep(p) && "Keep expected.");
+
+ /* keep the result */
+ cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
+ keepin[0] = sse_load;
+ be_new_Keep(cls, irg, block, 1, keepin);
+
+ return sse_load;
+ }
+
+ /* transform call modes */
+ if (mode_is_data(mode)) {
+ cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
+ mode = cls->mode;
+ }
+
+ return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
+}
+
+/**
+ * Transform the Projs from a Cmp.
+ */
+static ir_node *gen_Proj_Cmp(ir_node *node)
+{
+ /* normally Cmps are processed when looking at Cond nodes, but this case
+ * can happen in complicated Psi conditions */
+
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *cmp = get_Proj_pred(node);
+ long pnc = get_Proj_proj(node);
+ ir_node *cmp_left = get_Cmp_left(cmp);
+ ir_node *cmp_right = get_Cmp_right(cmp);
+ ir_node *new_cmp_left;
+ ir_node *new_cmp_right;
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_mode *cmp_mode = get_irn_mode(cmp_left);
+ ir_node *new_op;
+
+ assert(!mode_is_float(cmp_mode));
+
+ /* (a != b) -> (a ^ b) */
+ if(pnc == pn_Cmp_Lg) {
+ if(is_Const_0(cmp_left)) {
+ new_op = be_transform_node(cmp_right);
+ } else if(is_Const_0(cmp_right)) {
+ new_op = be_transform_node(cmp_left);
+ } else {
+ new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
+ }
+
+ return new_op;
+ }
+ /* TODO:
+ * (a == b) -> !(a ^ b)
+ * (a < 0) -> (a & 0x80000000) oder a >> 31
+ * (a >= 0) -> (a >> 31) ^ 1
+ */
+
+ if(!mode_is_signed(cmp_mode)) {
+ pnc |= ia32_pn_Cmp_Unsigned;
+ }
+
+ new_cmp_right = try_create_Immediate(cmp_right, 0);
+ if(new_cmp_right == NULL) {
+ new_cmp_right = try_create_Immediate(cmp_left, 0);
+ if(new_cmp_right != NULL) {
+ pnc = get_inversed_pnc(pnc);
+ new_cmp_left = be_transform_node(cmp_right);
+ }
+ } else {
+ new_cmp_left = be_transform_node(cmp_left);
+ }
+ if(new_cmp_right == NULL) {
+ new_cmp_left = be_transform_node(cmp_left);
+ new_cmp_right = be_transform_node(cmp_right);
+ }
+
+ new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
+ new_cmp_right, nomem, pnc);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
+
+ return new_op;
+}
+
+/**
+ * Transform and potentially renumber Proj nodes.
+ */
+static ir_node *gen_Proj(ir_node *node) {
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *pred = get_Proj_pred(node);
+ long proj = get_Proj_proj(node);
+
+ if (is_Store(pred) || be_is_FrameStore(pred)) {
+ if (proj == pn_Store_M) {
+ return be_transform_node(pred);
+ } else {
+ assert(0);
+ return new_r_Bad(irg);
+ }
+ } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
+ return gen_Proj_Load(node);
+ } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
+ return gen_Proj_DivMod(node);
+ } else if (is_CopyB(pred)) {
+ return gen_Proj_CopyB(node);
+ } else if (is_Quot(pred)) {
+ return gen_Proj_Quot(node);
+ } else if (is_ia32_l_vfdiv(pred)) {
+ return gen_Proj_l_vfdiv(node);
+ } else if (be_is_SubSP(pred)) {
+ return gen_Proj_be_SubSP(node);
+ } else if (be_is_AddSP(pred)) {
+ return gen_Proj_be_AddSP(node);
+ } else if (be_is_Call(pred)) {
+ return gen_Proj_be_Call(node);
+ } else if (is_Cmp(pred)) {
+ return gen_Proj_Cmp(node);
+ } else if (get_irn_op(pred) == op_Start) {
+ if (proj == pn_Start_X_initial_exec) {
+ ir_node *block = get_nodes_block(pred);
+ ir_node *jump;
+
+ /* we exchange the ProjX with a jump */
+ block = be_transform_node(block);
+ jump = new_rd_Jmp(dbgi, irg, block);
+ return jump;
+ }
+ if (node == be_get_old_anchor(anchor_tls)) {
+ return gen_Proj_tls(node);
+ }
+ } else {
+ ir_node *new_pred = be_transform_node(pred);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_mode *mode = get_irn_mode(node);
+ if (mode_needs_gp_reg(mode)) {
+ ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
+ get_Proj_proj(node));
+#ifdef DEBUG_libfirm
+ new_proj->node_nr = node->node_nr;
+#endif
+ return new_proj;
+ }
+ }
+
+ return be_duplicate_node(node);
+}
+