-
-
-void parse_asm_constraints(constraint_t *constraint, const char *c,
- bool is_output)
-{
- asm_constraint_flags_t flags = 0;
- char immediate_type = '\0';
- unsigned limited = 0;
- const arch_register_class_t *cls = NULL;
- bool memory_possible = false;
- bool all_registers_allowed = false;
- int p;
- int same_as = -1;
-
- memset(constraint, 0, sizeof(constraint[0]));
- constraint->same_as = -1;
-
- if(*c == 0) {
- /* a memory constraint: no need to do anything in backend about it
- * (the dependencies are already respected by the memory edge of
- * the node) */
- return;
- }
-
- /* TODO: improve error messages with node and source info. (As users can
- * easily hit these) */
- while(*c != 0) {
- switch(*c) {
- case ' ':
- case '\t':
- case '\n':
- break;
-
- case '=':
- flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
- | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
- break;
-
- case '+':
- flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
- | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
- break;
-
- case '*':
- ++c;
- break;
- case '#':
- while(*c != 0 && *c != ',')
- ++c;
- break;
-
- case 'a':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX;
- break;
- case 'b':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EBX;
- break;
- case 'c':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_ECX;
- break;
- case 'd':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EDX;
- break;
- case 'D':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EDI;
- break;
- case 'S':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_ESI;
- break;
- case 'Q':
- case 'q':
- /* q means lower part of the regs only, this makes no
- * difference to Q for us (we only assign whole registers) */
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
- 1 << REG_EDX;
- break;
- case 'A':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EDX;
- break;
- case 'l':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
- 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
- 1 << REG_EBP;
- break;
-
- case 'R':
- case 'r':
- case 'p':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- all_registers_allowed = true;
- break;
-
- case 'f':
- case 't':
- case 'u':
- /* TODO: mark values so the x87 simulator knows about t and u */
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
- panic("multiple register classes not supported");
- cls = &ia32_reg_classes[CLASS_ia32_vfp];
- all_registers_allowed = true;
- break;
-
- case 'Y':
- case 'x':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
- panic("multiple register classes not supproted");
- cls = &ia32_reg_classes[CLASS_ia32_xmm];
- all_registers_allowed = true;
- break;
-
- case 'I':
- case 'J':
- case 'K':
- case 'L':
- case 'M':
- case 'N':
- case 'O':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- if (immediate_type != '\0')
- panic("multiple immediate types not supported");
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- immediate_type = *c;
- break;
- case 'n':
- case 'i':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- if (immediate_type != '\0')
- panic("multiple immediate types not supported");
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- immediate_type = 'i';
- break;
-
- case 'X':
- case 'g':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- if (immediate_type != '\0')
- panic("multiple immediate types not supported");
- immediate_type = 'i';
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- all_registers_allowed = true;
- memory_possible = true;
- break;
-
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- if (is_output)
- panic("can only specify same constraint on input");
-
- sscanf(c, "%d%n", &same_as, &p);
- if(same_as >= 0) {
- c += p;
- continue;
- }
- break;
-
- case 'm':
- case 'o':
- case 'V':
- /* memory constraint no need to do anything in backend about it
- * (the dependencies are already respected by the memory edge of
- * the node) */
- memory_possible = true;
- break;
-
- case 'E': /* no float consts yet */
- case 'F': /* no float consts yet */
- case 's': /* makes no sense on x86 */
- case '<': /* no autodecrement on x86 */
- case '>': /* no autoincrement on x86 */
- case 'C': /* sse constant not supported yet */
- case 'G': /* 80387 constant not supported yet */
- case 'y': /* we don't support mmx registers yet */
- case 'Z': /* not available in 32 bit mode */
- case 'e': /* not available in 32 bit mode */
- panic("unsupported asm constraint '%c' found in (%+F)",
- *c, current_ir_graph);
- break;
- default:
- panic("unknown asm constraint '%c' found in (%+F)", *c,
- current_ir_graph);
- break;
- }
- ++c;
- }
-
- if(same_as >= 0) {
- if (cls != NULL)
- panic("same as and register constraint not supported");
- if (immediate_type != '\0')
- panic("same as and immediate constraint not supported");
- }
-
- if (cls == NULL && same_as < 0) {
- if (!memory_possible)
- panic("no constraint specified for assembler input");
- }
-
- constraint->same_as = same_as;
- constraint->cls = cls;
- constraint->allowed_registers = limited;
- constraint->all_registers_allowed = all_registers_allowed;
- constraint->memory_possible = memory_possible;
- constraint->immediate_type = immediate_type;
-}
-
-const arch_register_req_t *make_register_req(const constraint_t *constraint,
- int n_outs, const arch_register_req_t **out_reqs, int pos)
-{
- struct obstack *obst = get_irg_obstack(current_ir_graph);
- int same_as = constraint->same_as;
- arch_register_req_t *req;
-
- if (same_as >= 0) {
- const arch_register_req_t *other_constr;
-
- if (same_as >= n_outs)
- panic("invalid output number in same_as constraint");
-
- other_constr = out_reqs[same_as];
-
- req = obstack_alloc(obst, sizeof(req[0]));
- req->cls = other_constr->cls;
- req->type = arch_register_req_type_should_be_same;
- req->limited = NULL;
- req->other_same = 1U << pos;
- req->other_different = 0;
-
- /* switch constraints. This is because in firm we have same_as
- * constraints on the output constraints while in the gcc asm syntax
- * they are specified on the input constraints */
- out_reqs[same_as] = req;
- return other_constr;
- }
-
- /* pure memory ops */
- if (constraint->cls == NULL) {
- return &no_register_req;
- }
-
- if (constraint->allowed_registers != 0
- && !constraint->all_registers_allowed) {
- unsigned *limited_ptr;
-
- req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
- memset(req, 0, sizeof(req[0]));
- limited_ptr = (unsigned*) (req+1);
-
- req->type = arch_register_req_type_limited;
- *limited_ptr = constraint->allowed_registers;
- req->limited = limited_ptr;
- } else {
- req = obstack_alloc(obst, sizeof(req[0]));
- memset(req, 0, sizeof(req[0]));
- req->type = arch_register_req_type_normal;
- }
- req->cls = constraint->cls;
-
- return req;
-}
-
-const arch_register_t *ia32_get_clobber_register(const char *clobber)
-{
- const arch_register_t *reg = NULL;
- int c;
- size_t r;
- const arch_register_class_t *cls;
-
- /* TODO: construct a hashmap instead of doing linear search for clobber
- * register */
- for(c = 0; c < N_CLASSES; ++c) {
- cls = & ia32_reg_classes[c];
- for(r = 0; r < cls->n_regs; ++r) {
- const arch_register_t *temp_reg = arch_register_for_index(cls, r);
- if(strcmp(temp_reg->name, clobber) == 0
- || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
- reg = temp_reg;
- break;
- }
- }
- if(reg != NULL)
- break;
- }
-
- return reg;
-}
-
-const arch_register_req_t *parse_clobber(const char *clobber)
-{
- struct obstack *obst = get_irg_obstack(current_ir_graph);
- const arch_register_t *reg = ia32_get_clobber_register(clobber);
- arch_register_req_t *req;
- unsigned *limited;
-
- if(reg == NULL) {
- panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
- }
-
- assert(reg->index < 32);
-
- limited = obstack_alloc(obst, sizeof(limited[0]));
- *limited = 1 << reg->index;
-
- req = obstack_alloc(obst, sizeof(req[0]));
- memset(req, 0, sizeof(req[0]));
- req->type = arch_register_req_type_limited;
- req->cls = arch_register_get_class(reg);
- req->limited = limited;
-
- return req;
-}
-
-/**
- * generates code for a ASM node
- */
-static ir_node *gen_ASM(ir_node *node)
-{
- ir_graph *irg = current_ir_graph;
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- int i, arity;
- int out_idx;
- ir_node **in;
- ir_node *new_node;
- int out_arity;
- int n_out_constraints;
- int n_clobbers;
- const arch_register_req_t **out_reg_reqs;
- const arch_register_req_t **in_reg_reqs;
- ia32_asm_reg_t *register_map;
- unsigned reg_map_size = 0;
- struct obstack *obst;
- const ir_asm_constraint *in_constraints;
- const ir_asm_constraint *out_constraints;
- ident **clobbers;
- bool clobbers_flags = false;
-
- /* workaround for lots of buggy code out there as most people think volatile
- * asm is enough for everything and forget the flags (linux kernel, etc.)
- */
- if (get_irn_pinned(node) == op_pin_state_pinned) {
- clobbers_flags = true;
- }
-
- arity = get_irn_arity(node);
- in = alloca(arity * sizeof(in[0]));
- memset(in, 0, arity * sizeof(in[0]));
-
- clobbers = get_ASM_clobbers(node);
- n_clobbers = 0;
- for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
- const char *c = get_id_str(clobbers[i]);
- if (strcmp(c, "memory") == 0)
- continue;
- if (strcmp(c, "cc") == 0) {
- clobbers_flags = true;
- continue;
- }
- n_clobbers++;
- }
- n_out_constraints = get_ASM_n_output_constraints(node);
- out_arity = n_out_constraints + n_clobbers;
-
- in_constraints = get_ASM_input_constraints(node);
- out_constraints = get_ASM_output_constraints(node);
-
- /* determine size of register_map */
- for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
- const ir_asm_constraint *constraint = &out_constraints[out_idx];
- if (constraint->pos > reg_map_size)
- reg_map_size = constraint->pos;
- }
- for(i = 0; i < arity; ++i) {
- const ir_asm_constraint *constraint = &in_constraints[i];
- if(constraint->pos > reg_map_size)
- reg_map_size = constraint->pos;
- }
- ++reg_map_size;
-
- obst = get_irg_obstack(irg);
- register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
- memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
-
- /* construct output constraints */
- out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
-
- for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
- const ir_asm_constraint *constraint = &out_constraints[out_idx];
- const char *c = get_id_str(constraint->constraint);
- unsigned pos = constraint->pos;
- constraint_t parsed_constraint;
- const arch_register_req_t *req;
-
- parse_asm_constraints(&parsed_constraint, c, true);
- req = make_register_req(&parsed_constraint, n_out_constraints,
- out_reg_reqs, out_idx);
- out_reg_reqs[out_idx] = req;
-
- register_map[pos].use_input = false;
- register_map[pos].valid = true;
- register_map[pos].memory = false;
- register_map[pos].inout_pos = out_idx;
- register_map[pos].mode = constraint->mode;
- }
-
- /* inputs + input constraints */
- in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
- for(i = 0; i < arity; ++i) {
- ir_node *pred = get_irn_n(node, i);
- const ir_asm_constraint *constraint = &in_constraints[i];
- ident *constr_id = constraint->constraint;
- const char *c = get_id_str(constr_id);
- unsigned pos = constraint->pos;
- bool is_memory_op = false;
- ir_node *input = NULL;
- constraint_t parsed_constraint;
- const arch_register_req_t *req;
-
- parse_asm_constraints(&parsed_constraint, c, false);
- req = make_register_req(&parsed_constraint, n_out_constraints,
- out_reg_reqs, i);
- in_reg_reqs[i] = req;
-
- if (parsed_constraint.immediate_type != '\0') {
- char imm_type = parsed_constraint.immediate_type;
- input = try_create_Immediate(pred, imm_type);
- }
-
- if (input == NULL) {
- ir_node *pred = get_irn_n(node, i);
- input = be_transform_node(pred);
-
- if (parsed_constraint.cls == NULL
- && parsed_constraint.same_as < 0) {
- is_memory_op = true;
- } else if(parsed_constraint.memory_possible) {
- /* TODO: match Load or Load/Store if memory possible is set */
- }
- }
- in[i] = input;
-
- register_map[pos].use_input = true;
- register_map[pos].valid = true;
- register_map[pos].memory = is_memory_op;
- register_map[pos].inout_pos = i;
- register_map[pos].mode = constraint->mode;
- }
-
- /* parse clobbers */
- for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
- const char *c = get_id_str(clobbers[i]);
- const arch_register_req_t *req;
-
- if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
- continue;
-
- req = parse_clobber(c);
- out_reg_reqs[out_idx] = req;
- ++out_idx;
- }
-
- new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
- get_ASM_text(node), register_map);
-
- set_ia32_out_req_all(new_node, out_reg_reqs);
- set_ia32_in_req_all(new_node, in_reg_reqs);
-
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
-
- return new_node;
-}
-