+ /* store must be the only user of the val node */
+ if(get_irn_n_edges(val) > 1)
+ return NULL;
+
+ switch(get_irn_opcode(val)) {
+ case iro_Add:
+ op1 = get_Add_left(val);
+ op2 = get_Add_right(val);
+ if(is_Const_1(op2)) {
+ new_node = dest_am_unop(val, op1, mem, ptr, mode,
+ new_rd_ia32_IncMem);
+ break;
+ } else if(is_Const_Minus_1(op2)) {
+ new_node = dest_am_unop(val, op1, mem, ptr, mode,
+ new_rd_ia32_DecMem);
+ break;
+ }
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
+ break;
+ case iro_Sub:
+ op1 = get_Sub_left(val);
+ op2 = get_Sub_right(val);
+ if(is_Const(op2)) {
+ ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
+ "found\n");
+ }
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
+ break;
+ case iro_And:
+ op1 = get_And_left(val);
+ op2 = get_And_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
+ break;
+ case iro_Or:
+ op1 = get_Or_left(val);
+ op2 = get_Or_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
+ break;
+ case iro_Eor:
+ op1 = get_Eor_left(val);
+ op2 = get_Eor_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
+ break;
+ case iro_Shl:
+ op1 = get_Shl_left(val);
+ op2 = get_Shl_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
+ break;
+ case iro_Shr:
+ op1 = get_Shr_left(val);
+ op2 = get_Shr_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
+ break;
+ case iro_Shrs:
+ op1 = get_Shrs_left(val);
+ op2 = get_Shrs_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
+ break;
+ case iro_Rot:
+ op1 = get_Rot_left(val);
+ op2 = get_Rot_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
+ break;
+ /* TODO: match ROR patterns... */
+ case iro_Minus:
+ op1 = get_Minus_op(val);
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
+ break;
+ case iro_Not:
+ /* should be lowered already */
+ assert(mode != mode_b);
+ op1 = get_Not_op(val);
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
+ break;
+ default:
+ return NULL;
+ }
+
+ return new_node;
+}
+
+/**
+ * Transforms a Store.
+ *
+ * @return the created ia32 Store node
+ */
+static ir_node *gen_Store(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *ptr = get_Store_ptr(node);
+ ir_node *base;
+ ir_node *index;
+ ir_node *val = get_Store_value(node);
+ ir_node *new_val;
+ ir_node *mem = get_Store_mem(node);
+ ir_node *new_mem = be_transform_node(mem);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_mode *mode = get_irn_mode(val);
+ ir_node *new_op;
+ ia32_address_t addr;
+
+ /* check for destination address mode */
+ new_op = try_create_dest_am(node);
+ if(new_op != NULL)
+ return new_op;
+
+ /* construct store address */
+ memset(&addr, 0, sizeof(addr));
+ ia32_create_address_mode(&addr, ptr, 0);
+ base = addr.base;
+ index = addr.index;