+ return ia32_new_Unknown_vfp(env->cg);
+ } else if (mode_needs_gp_reg(mode)) {
+ return ia32_new_Unknown_gp(env->cg);
+ } else {
+ assert(0 && "unsupported Unknown-Mode");
+ }
+
+ return NULL;
+}
+
+/**
+ * Change some phi modes
+ */
+static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *phi;
+ int i, arity;
+
+ if(mode_needs_gp_reg(mode)) {
+ /* we shouldn't have any 64bit stuff around anymore */
+ assert(get_mode_size_bits(mode) <= 32);
+ /* all integer operations are on 32bit registers now */
+ mode = mode_Iu;
+ } else if(mode_is_float(mode)) {
+ assert(mode == mode_D || mode == mode_F);
+ if (USE_SSE2(env->cg)) {
+ mode = mode_xmm;
+ } else {
+ mode = mode_vfp;
+ }
+ }
+
+ /* phi nodes allow loops, so we use the old arguments for now
+ * and fix this later */
+ phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
+ copy_node_attr(node, phi);
+ duplicate_deps(env, node, phi);
+
+ set_new_node(node, phi);
+
+ /* put the preds in the worklist */
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *pred = get_irn_n(node, i);
+ pdeq_putr(env->worklist, pred);
+ }
+
+ return phi;
+}
+
+/**********************************************************************
+ * _ _ _
+ * | | | | | |
+ * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
+ * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
+ * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
+ * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
+ *
+ **********************************************************************/
+
+/* These nodes are created in intrinsic lowering (64bit -> 32bit) */
+
+typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
+ ir_node *mem);
+
+typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
+ ir_node *val, ir_node *mem);
+
+/**
+ * Transforms a lowered Load into a "real" one.
+ */
+static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *ptr = get_irn_n(node, 0);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *mem = get_irn_n(node, 1);
+ ir_node *new_mem = transform_node(env, mem);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *new_op;
+
+ /*
+ Could be that we have SSE2 unit, but due to 64Bit Div/Conv
+ lowering we have x87 nodes, so we need to enforce simulation.
+ */
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (fp_unit == fp_x87)
+ FORCE_x87(env->cg);
+ }
+
+ new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_am_OB);
+ set_ia32_am_offs_int(new_op, 0);
+ set_ia32_am_scale(new_op, 1);
+ set_ia32_am_sc(new_op, get_ia32_am_sc(node));
+ if (is_ia32_am_sc_sign(node))
+ set_ia32_am_sc_sign(new_op);
+ set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
+ if (is_ia32_use_frame(node)) {
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+ }
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+/**
+* Transforms a lowered Store into a "real" one.
+*/
+static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *ptr = get_irn_n(node, 0);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *val = get_irn_n(node, 1);
+ ir_node *new_val = transform_node(env, val);
+ ir_node *mem = get_irn_n(node, 2);
+ ir_node *new_mem = transform_node(env, mem);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *new_op;
+ long am_offs;
+ ia32_am_flavour_t am_flav = ia32_B;
+
+ /*
+ Could be that we have SSE2 unit, but due to 64Bit Div/Conv
+ lowering we have x87 nodes, so we need to enforce simulation.
+ */
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (fp_unit == fp_x87)
+ FORCE_x87(env->cg);
+ }
+
+ new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+
+ if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
+ am_flav |= ia32_O;
+ add_ia32_am_offs_int(new_op, am_offs);
+ }
+
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, am_flav);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+
+/**
+ * Transforms an ia32_l_XXX into a "real" XXX node
+ *
+ * @param env The transformation environment
+ * @return the created ia32 XXX node
+ */
+#define GEN_LOWERED_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ ir_mode *mode = get_irn_mode(node); \
+ if (mode_is_float(mode)) \
+ FP_USED(env->cg); \
+ return gen_binop(env, node, get_binop_left(node), \
+ get_binop_right(node), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_x87_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ ir_node *new_op; \
+ FORCE_x87(env->cg); \
+ new_op = gen_binop_float(env, node, get_binop_left(node), \
+ get_binop_right(node), new_rd_ia32_##op); \
+ return new_op; \
+ }
+
+#define GEN_LOWERED_UNOP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_SHIFT_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_shift_binop(env, node, get_binop_left(node), \
+ get_binop_right(node), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_LOAD(op, fp_unit) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \