+ if (mode_is_float(src_mode)) {
+ /* we convert from float ... */
+ if (mode_is_float(tgt_mode)) {
+ /* ... to float */
+ if (USE_SSE2(env->cg)) {
+ DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
+ res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ set_ia32_ls_mode(res, tgt_mode);
+ } else {
+ // Matze: TODO what about strict convs?
+ DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
+ DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
+ return new_op;
+ }
+ } else {
+ /* ... to int */
+ DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
+ if (USE_SSE2(env->cg)) {
+ res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ set_ia32_ls_mode(res, src_mode);
+ } else {
+ return gen_x87_fp_to_gp(env, node);
+ }
+ }
+ } else {
+ /* we convert from int ... */
+ if (mode_is_float(tgt_mode)) {
+ FP_USED(env->cg);
+ /* ... to float */
+ DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
+ if (USE_SSE2(env->cg)) {
+ res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ set_ia32_ls_mode(res, tgt_mode);
+ if(src_bits == 32) {
+ set_ia32_am_support(res, ia32_am_Source);
+ }
+ } else {
+ return gen_x87_gp_to_fp(env, node, src_mode);
+ }
+ } else {
+ /* to int */
+ ir_mode *smaller_mode;
+ int smaller_bits;
+
+ if (src_bits == tgt_bits) {
+ DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
+ return new_op;
+ }
+
+ if (src_bits < tgt_bits) {
+ smaller_mode = src_mode;
+ smaller_bits = src_bits;
+ } else {
+ smaller_mode = tgt_mode;
+ smaller_bits = tgt_bits;
+ }
+
+ /*
+ The following is not correct, we can't change the mode,
+ maybe others are using the load too
+ better move this to a separate phase!
+ */
+#if 0
+ /* ... to int */
+ if(is_Proj(new_op)) {
+ /* load operations do already sign/zero extend, so we have
+ * nothing left to do */
+ ir_node *pred = get_Proj_pred(new_op);
+ if(is_ia32_Load(pred)) {
+ set_ia32_ls_mode(pred, smaller_mode);
+ return new_op;
+ }
+ }
+#endif /* if 0 */
+
+ DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
+ if (smaller_bits == 8) {
+ res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ set_ia32_ls_mode(res, smaller_mode);
+ } else {
+ res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ set_ia32_ls_mode(res, smaller_mode);
+ }
+ set_ia32_am_support(res, ia32_am_Source);
+ }
+ }
+
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
+
+ return res;
+}
+
+
+
+/********************************************
+ * _ _
+ * | | | |
+ * | |__ ___ _ __ ___ __| | ___ ___
+ * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
+ * | |_) | __/ | | | (_) | (_| | __/\__ \
+ * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
+ *
+ ********************************************/
+
+static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *new_op = NULL;
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+ ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
+ ir_mode *load_mode = get_irn_mode(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_mode *proj_mode;
+ long pn_res;
+
+ if (mode_is_float(load_mode)) {
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg)) {
+ new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
+ pn_res = pn_ia32_xLoad_res;
+ proj_mode = mode_xmm;
+ } else {
+ new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
+ pn_res = pn_ia32_vfld_res;
+ proj_mode = mode_vfp;
+ }
+ } else {
+ new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
+ proj_mode = mode_Iu;
+ pn_res = pn_ia32_Load_res;
+ }
+
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_am_B);
+ set_ia32_ls_mode(new_op, load_mode);
+ set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
+}
+
+/**
+ * Transforms a FrameAddr into an ia32 Add.
+ */
+static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
+ ir_node *new_op = transform_node(env, op);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *res;
+
+ res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
+ set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
+ set_ia32_am_support(res, ia32_am_Full);
+ set_ia32_use_frame(res);
+ set_ia32_am_flavour(res, ia32_am_OB);
+
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
+
+ return res;
+}
+
+/**
+ * Transforms a FrameLoad into an ia32 Load.
+ */
+static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
+ ir_node *new_mem = transform_node(env, mem);
+ ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *new_op = NULL;
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
+ ir_mode *mode = get_type_mode(get_entity_type(ent));
+ ir_node *projs[pn_Load_max];
+
+ ia32_collect_Projs(node, projs, pn_Load_max);
+
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg)) {
+ new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
+ }
+ else {
+ new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
+ }
+ }
+ else {
+ new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
+ }
+
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_am_B);
+ set_ia32_ls_mode(new_op, mode);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+
+/**
+ * Transforms a FrameStore into an ia32 Store.
+ */
+static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
+ ir_node *new_mem = transform_node(env, mem);
+ ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
+ ir_node *new_val = transform_node(env, val);
+ ir_node *new_op = NULL;
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
+ ir_mode *mode = get_irn_mode(val);
+
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg)) {
+ new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ } else {
+ new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ }
+ } else if (get_mode_size_bits(mode) == 8) {
+ new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ } else {
+ new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ }
+
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, ia32_am_B);
+ set_ia32_ls_mode(new_op, mode);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+/**
+ * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
+ */
+static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
+ ir_graph *irg = env->irg;
+ ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
+ ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
+ ir_entity *ent = get_irg_entity(irg);
+ ir_type *tp = get_entity_type(ent);
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_type *res_type;
+ ir_mode *mode;
+ ir_node *frame, *sse_store, *fld, *mproj, *barrier;
+ ir_node *new_barrier, *new_ret_val, *new_ret_mem;
+ ir_node **in;
+ int pn_ret_val, pn_ret_mem, arity, i;
+
+ assert(ret_val != NULL);
+ if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
+ return duplicate_node(env, node);
+ }
+
+ res_type = get_method_res_type(tp, 0);
+
+ if (! is_Primitive_type(res_type)) {
+ return duplicate_node(env, node);
+ }
+
+ mode = get_type_mode(res_type);
+ if (! mode_is_float(mode)) {
+ return duplicate_node(env, node);
+ }
+
+ assert(get_method_n_ress(tp) == 1);
+
+ pn_ret_val = get_Proj_proj(ret_val);
+ pn_ret_mem = get_Proj_proj(ret_mem);
+
+ /* get the Barrier */
+ barrier = get_Proj_pred(ret_val);
+
+ /* get result input of the Barrier */
+ ret_val = get_irn_n(barrier, pn_ret_val);
+ new_ret_val = transform_node(env, ret_val);
+
+ /* get memory input of the Barrier */
+ ret_mem = get_irn_n(barrier, pn_ret_mem);
+ new_ret_mem = transform_node(env, ret_mem);
+
+ frame = get_irg_frame(irg);
+
+ dbgi = get_irn_dbg_info(barrier);
+ block = transform_node(env, get_nodes_block(barrier));
+
+ /* store xmm0 onto stack */
+ sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
+ set_ia32_ls_mode(sse_store, mode);
+ set_ia32_op_type(sse_store, ia32_AddrModeD);
+ set_ia32_use_frame(sse_store);
+ set_ia32_am_flavour(sse_store, ia32_am_B);
+ set_ia32_am_support(sse_store, ia32_am_Dest);
+
+ /* load into st0 */
+ fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
+ set_ia32_ls_mode(fld, mode);
+ set_ia32_op_type(fld, ia32_AddrModeS);
+ set_ia32_use_frame(fld);
+ set_ia32_am_flavour(fld, ia32_am_B);
+ set_ia32_am_support(fld, ia32_am_Source);
+
+ mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
+ fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
+ arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
+
+ /* create a new barrier */
+ arity = get_irn_arity(barrier);
+ in = alloca(arity * sizeof(in[0]));
+ for (i = 0; i < arity; ++i) {
+ ir_node *new_in;
+
+ if (i == pn_ret_val) {
+ new_in = fld;
+ } else if (i == pn_ret_mem) {
+ new_in = mproj;
+ } else {
+ ir_node *in = get_irn_n(barrier, i);
+ new_in = transform_node(env, in);
+ }
+ in[i] = new_in;
+ }
+
+ new_barrier = new_ir_node(dbgi, irg, block,
+ get_irn_op(barrier), get_irn_mode(barrier),
+ arity, in);
+ copy_node_attr(barrier, new_barrier);
+ duplicate_deps(env, barrier, new_barrier);
+ set_new_node(barrier, new_barrier);
+ mark_irn_visited(barrier);
+
+ /* transform normally */
+ return duplicate_node(env, node);
+}
+
+/**
+ * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
+ */
+static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
+ ir_node *new_sz = transform_node(env, sz);
+ ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
+ ir_node *new_sp = transform_node(env, sp);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *new_op;
+
+ /* ia32 stack grows in reverse direction, make a SubSP */
+ new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ fold_immediate(env, new_op, 2, 3);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+/**
+ * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
+ */
+static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
+ ir_node *new_sz = transform_node(env, sz);
+ ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
+ ir_node *new_sp = transform_node(env, sp);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *new_op;
+
+ /* ia32 stack grows in reverse direction, make an AddSP */
+ new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ fold_immediate(env, new_op, 2, 3);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+/**
+ * This function just sets the register for the Unknown node
+ * as this is not done during register allocation because Unknown
+ * is an "ignore" node.
+ */
+static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
+ ir_mode *mode = get_irn_mode(node);
+
+ if (mode_is_float(mode)) {
+ if (USE_SSE2(env->cg))
+ return ia32_new_Unknown_xmm(env->cg);
+ else
+ return ia32_new_Unknown_vfp(env->cg);
+ } else if (mode_needs_gp_reg(mode)) {
+ return ia32_new_Unknown_gp(env->cg);
+ } else {
+ assert(0 && "unsupported Unknown-Mode");
+ }
+
+ return NULL;
+}
+
+/**
+ * Change some phi modes
+ */
+static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *phi;
+ int i, arity;
+
+ if(mode_needs_gp_reg(mode)) {
+ /* we shouldn't have any 64bit stuff around anymore */
+ assert(get_mode_size_bits(mode) <= 32);
+ /* all integer operations are on 32bit registers now */
+ mode = mode_Iu;
+ } else if(mode_is_float(mode)) {
+ assert(mode == mode_D || mode == mode_F);
+ if (USE_SSE2(env->cg)) {
+ mode = mode_xmm;
+ } else {
+ mode = mode_vfp;
+ }
+ }
+
+ /* phi nodes allow loops, so we use the old arguments for now
+ * and fix this later */
+ phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
+ copy_node_attr(node, phi);
+ duplicate_deps(env, node, phi);
+
+ set_new_node(node, phi);
+
+ /* put the preds in the worklist */
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *pred = get_irn_n(node, i);
+ pdeq_putr(env->worklist, pred);
+ }
+
+ return phi;
+}
+
+/**********************************************************************
+ * _ _ _
+ * | | | | | |
+ * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
+ * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
+ * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
+ * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
+ *
+ **********************************************************************/
+
+/* These nodes are created in intrinsic lowering (64bit -> 32bit) */
+
+typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
+ ir_node *mem);
+
+typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
+ ir_node *val, ir_node *mem);
+
+/**
+ * Transforms a lowered Load into a "real" one.
+ */
+static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *ptr = get_irn_n(node, 0);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *mem = get_irn_n(node, 1);
+ ir_node *new_mem = transform_node(env, mem);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *new_op;
+
+ /*
+ Could be that we have SSE2 unit, but due to 64Bit Div/Conv
+ lowering we have x87 nodes, so we need to enforce simulation.
+ */
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (fp_unit == fp_x87)
+ FORCE_x87(env->cg);
+ }
+
+ new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_am_OB);
+ set_ia32_am_offs_int(new_op, 0);
+ set_ia32_am_scale(new_op, 1);
+ set_ia32_am_sc(new_op, get_ia32_am_sc(node));
+ if (is_ia32_am_sc_sign(node))
+ set_ia32_am_sc_sign(new_op);
+ set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
+ if (is_ia32_use_frame(node)) {
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+ }
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+/**
+* Transforms a lowered Store into a "real" one.
+*/
+static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *ptr = get_irn_n(node, 0);
+ ir_node *new_ptr = transform_node(env, ptr);
+ ir_node *val = get_irn_n(node, 1);
+ ir_node *new_val = transform_node(env, val);
+ ir_node *mem = get_irn_n(node, 2);
+ ir_node *new_mem = transform_node(env, mem);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *new_op;
+ long am_offs;
+ ia32_am_flavour_t am_flav = ia32_B;
+
+ /*
+ Could be that we have SSE2 unit, but due to 64Bit Div/Conv
+ lowering we have x87 nodes, so we need to enforce simulation.
+ */
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (fp_unit == fp_x87)
+ FORCE_x87(env->cg);
+ }
+
+ new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+
+ if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
+ am_flav |= ia32_O;
+ add_ia32_am_offs_int(new_op, am_offs);
+ }
+
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, am_flav);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+
+/**
+ * Transforms an ia32_l_XXX into a "real" XXX node
+ *
+ * @param env The transformation environment
+ * @return the created ia32 XXX node
+ */
+#define GEN_LOWERED_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ ir_mode *mode = get_irn_mode(node); \
+ if (mode_is_float(mode)) \
+ FP_USED(env->cg); \
+ return gen_binop(env, node, get_binop_left(node), \
+ get_binop_right(node), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_x87_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ ir_node *new_op; \
+ FORCE_x87(env->cg); \
+ new_op = gen_binop_float(env, node, get_binop_left(node), \
+ get_binop_right(node), new_rd_ia32_##op); \
+ return new_op; \
+ }
+
+#define GEN_LOWERED_UNOP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_SHIFT_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_shift_binop(env, node, get_binop_left(node), \
+ get_binop_right(node), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_LOAD(op, fp_unit) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
+ }
+
+#define GEN_LOWERED_STORE(op, fp_unit) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
+ return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
+ }
+
+GEN_LOWERED_OP(Adc)
+GEN_LOWERED_OP(Add)
+GEN_LOWERED_OP(Sbb)
+GEN_LOWERED_OP(Sub)
+GEN_LOWERED_OP(IMul)
+GEN_LOWERED_OP(Xor)
+GEN_LOWERED_x87_OP(vfprem)
+GEN_LOWERED_x87_OP(vfmul)
+GEN_LOWERED_x87_OP(vfsub)
+
+GEN_LOWERED_UNOP(Neg)
+
+GEN_LOWERED_LOAD(vfild, fp_x87)
+GEN_LOWERED_LOAD(Load, fp_none)
+/*GEN_LOWERED_STORE(vfist, fp_x87)
+ *TODO
+ */
+GEN_LOWERED_STORE(Store, fp_none)
+
+static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *left = get_binop_left(node);
+ ir_node *new_left = transform_node(env, left);
+ ir_node *right = get_binop_right(node);
+ ir_node *new_right = transform_node(env, right);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *vfdiv;
+
+ vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
+ clear_ia32_commutative(vfdiv);
+ set_ia32_am_support(vfdiv, ia32_am_Source);
+ fold_immediate(env, vfdiv, 2, 3);
+
+ SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
+
+ FORCE_x87(env->cg);
+
+ return vfdiv;
+}
+
+/**
+ * Transforms a l_MulS into a "real" MulS node.
+ *
+ * @param env The transformation environment
+ * @return the created ia32 Mul node
+ */
+static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *left = get_binop_left(node);
+ ir_node *new_left = transform_node(env, left);
+ ir_node *right = get_binop_right(node);
+ ir_node *new_right = transform_node(env, right);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *in[2];
+
+ /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
+ /* and then skip the result Proj, because all needed Projs are already there. */
+ ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
+ clear_ia32_commutative(muls);
+ set_ia32_am_support(muls, ia32_am_Source);
+ fold_immediate(env, muls, 2, 3);
+
+ /* check if EAX and EDX proj exist, add missing one */
+ in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
+ in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
+
+ SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
+
+ return muls;
+}
+
+GEN_LOWERED_SHIFT_OP(Shl)
+GEN_LOWERED_SHIFT_OP(Shr)
+GEN_LOWERED_SHIFT_OP(Sar)
+
+/**
+ * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
+ * op1 - target to be shifted
+ * op2 - contains bits to be shifted into target
+ * op3 - shift count
+ * Only op3 can be an immediate.
+ */
+static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
+ ir_node *op1, ir_node *op2,
+ ir_node *count)
+{
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *new_op1 = transform_node(env, op1);
+ ir_node *new_op2 = transform_node(env, op2);
+ ir_node *new_count = transform_node(env, count);
+ ir_node *new_op = NULL;
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *imm_op;
+ tarval *tv;
+
+ assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
+
+ /* Check if immediate optimization is on and */
+ /* if it's an operation with immediate. */
+ imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
+
+ /* Limit imm_op within range imm8 */
+ if (imm_op) {
+ tv = get_ia32_Immop_tarval(imm_op);
+
+ if (tv) {
+ tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
+ set_ia32_Immop_tarval(imm_op, tv);
+ }
+ else {
+ imm_op = NULL;
+ }
+ }
+
+ /* integer operations */
+ if (imm_op) {
+ /* This is ShiftD with const */
+ DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
+
+ if (is_ia32_l_ShlD(node))
+ new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
+ new_op1, new_op2, noreg, nomem);
+ else
+ new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
+ new_op1, new_op2, noreg, nomem);
+ copy_ia32_Immop_attr(new_op, imm_op);
+ }
+ else {
+ /* This is a normal ShiftD */
+ DB((dbg, LEVEL_1, "ShiftD binop ..."));
+ if (is_ia32_l_ShlD(node))
+ new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
+ new_op1, new_op2, new_count, nomem);
+ else
+ new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
+ new_op1, new_op2, new_count, nomem);
+ }
+
+ /* set AM support */
+ // Matze: node has unsupported format (6inputs)
+ //set_ia32_am_support(new_op, ia32_am_Dest);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ set_ia32_emit_cl(new_op);
+
+ return new_op;
+}
+
+static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
+ return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
+ get_irn_n(node, 1), get_irn_n(node, 2));
+}
+
+static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
+ return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
+ get_irn_n(node, 1), get_irn_n(node, 2));
+}
+
+/**
+ * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
+ */
+static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *val = get_irn_n(node, 1);
+ ir_node *new_val = transform_node(env, val);
+ ia32_code_gen_t *cg = env->cg;
+ ir_node *res = NULL;
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi;
+ ir_node *noreg, *new_ptr, *new_mem;
+ ir_node *ptr, *mem;
+
+ if (USE_SSE2(cg)) {
+ return new_val;
+ }
+
+ mem = get_irn_n(node, 2);
+ new_mem = transform_node(env, mem);
+ ptr = get_irn_n(node, 0);
+ new_ptr = transform_node(env, ptr);
+ noreg = ia32_new_NoReg_gp(cg);
+ dbgi = get_irn_dbg_info(node);
+
+ /* Store x87 -> MEM */
+ res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ set_ia32_frame_ent(res, get_ia32_frame_ent(node));
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(node));
+ set_ia32_am_support(res, ia32_am_Dest);
+ set_ia32_am_flavour(res, ia32_B);
+ set_ia32_op_type(res, ia32_AddrModeD);
+
+ /* Load MEM -> SSE */
+ res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
+ set_ia32_frame_ent(res, get_ia32_frame_ent(node));
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(node));
+ set_ia32_am_support(res, ia32_am_Source);
+ set_ia32_am_flavour(res, ia32_B);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
+
+ return res;
+}
+
+/**
+ * In case SSE Unit is used, the node is transformed into a xStore + vfld.
+ */
+static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *val = get_irn_n(node, 1);
+ ir_node *new_val = transform_node(env, val);
+ ia32_code_gen_t *cg = env->cg;
+ ir_graph *irg = env->irg;
+ ir_node *res = NULL;
+ ir_entity *fent = get_ia32_frame_ent(node);
+ ir_mode *lsmode = get_ia32_ls_mode(node);
+ int offs = 0;
+ ir_node *noreg, *new_ptr, *new_mem;
+ ir_node *ptr, *mem;
+ dbg_info *dbgi;
+
+ if (! USE_SSE2(cg)) {
+ /* SSE unit is not used -> skip this node. */
+ return new_val;
+ }
+
+ ptr = get_irn_n(node, 0);
+ new_ptr = transform_node(env, ptr);
+ mem = get_irn_n(node, 2);
+ new_mem = transform_node(env, mem);
+ noreg = ia32_new_NoReg_gp(cg);
+ dbgi = get_irn_dbg_info(node);
+
+ /* Store SSE -> MEM */
+ if (is_ia32_xLoad(skip_Proj(new_val))) {
+ ir_node *ld = skip_Proj(new_val);
+
+ /* we can vfld the value directly into the fpu */
+ fent = get_ia32_frame_ent(ld);
+ ptr = get_irn_n(ld, 0);
+ offs = get_ia32_am_offs_int(ld);
+ } else {
+ res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ set_ia32_frame_ent(res, fent);
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, lsmode);
+ set_ia32_am_support(res, ia32_am_Dest);
+ set_ia32_am_flavour(res, ia32_B);
+ set_ia32_op_type(res, ia32_AddrModeD);
+ mem = res;
+ }
+
+ /* Load MEM -> x87 */
+ res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
+ set_ia32_frame_ent(res, fent);
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, lsmode);
+ add_ia32_am_offs_int(res, offs);
+ set_ia32_am_support(res, ia32_am_Source);
+ set_ia32_am_flavour(res, ia32_B);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
+
+ return res;
+}
+
+/*********************************************************
+ * _ _ _
+ * (_) | | (_)
+ * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
+ * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
+ * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
+ * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
+ *
+ *********************************************************/
+
+/**
+ * the BAD transformer.
+ */
+static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
+ panic("No transform function for %+F available.\n", node);
+ return NULL;
+}
+
+static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
+ /* end has to be duplicated manually because we need a dynamic in array */
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ int i, arity;
+ ir_node *new_end;
+
+ new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
+ copy_node_attr(node, new_end);
+ duplicate_deps(env, node, new_end);
+
+ set_irg_end(irg, new_end);
+ set_new_node(new_end, new_end);
+
+ /* transform preds */
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ ir_node *new_in = transform_node(env, in);
+
+ add_End_keepalive(new_end, new_in);
+ }
+
+ return new_end;
+}
+
+static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *start_block = env->old_anchors[anchor_start_block];
+ ir_node *block;
+ int i, arity;
+
+ /*
+ * We replace the ProjX from the start node with a jump,
+ * so the startblock has no preds anymore now
+ */
+ if (node == start_block) {
+ return new_rd_Block(dbgi, irg, 0, NULL);
+ }
+
+ /* we use the old blocks for now, because jumps allow cycles in the graph
+ * we have to fix this later */
+ block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
+ get_irn_arity(node), get_irn_in(node) + 1);
+ copy_node_attr(node, block);
+
+#ifdef DEBUG_libfirm
+ block->node_nr = node->node_nr;
+#endif
+ set_new_node(node, block);
+
+ /* put the preds in the worklist */
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ pdeq_putr(env->worklist, in);
+ }
+
+ return block;
+}
+
+static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ if (proj == pn_be_AddSP_res) {
+ ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
+ arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
+ return res;
+ } else if (proj == pn_be_AddSP_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ if (proj == pn_be_SubSP_res) {
+ ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
+ arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
+ return res;
+ } else if (proj == pn_be_SubSP_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+
+ /* renumber the proj */
+ if (is_ia32_Load(new_pred)) {
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
+ }
+ } else if (is_ia32_xLoad(new_pred)) {
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
+ }
+ } else if (is_ia32_vfld(new_pred)) {
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
+ }
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, get_irn_mode(node));
+}
+
+static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
+
+ switch (get_irn_opcode(pred)) {
+ case iro_Div:
+ switch (proj) {
+ case pn_Div_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
+ case pn_Div_res:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
+ default:
+ break;
+ }
+ break;
+ case iro_Mod:
+ switch (proj) {
+ case pn_Mod_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
+ case pn_Mod_res:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
+ default:
+ break;
+ }
+ break;
+ case iro_DivMod:
+ switch (proj) {
+ case pn_DivMod_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
+ case pn_DivMod_res_div:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
+ case pn_DivMod_res_mod:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, mode);
+}
+
+static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch(proj) {
+ case pn_CopyB_M_regular:
+ if (is_ia32_CopyB_i(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
+ } else if (is_ia32_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
+ }
+ break;
+ default:
+ break;
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, mode);
+}
+
+static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch (proj) {
+ case pn_ia32_l_vfdiv_M:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
+ case pn_ia32_l_vfdiv_res:
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ default:
+ assert(0);
+ }
+
+ return new_rd_Unknown(irg, mode);
+}
+
+static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = transform_node(env, pred);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ long proj = get_Proj_proj(node);
+
+ switch(proj) {
+ case pn_Quot_M:
+ if (is_ia32_xDiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
+ } else if (is_ia32_vfdiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
+ }
+ break;
+ case pn_Quot_res:
+ if (is_ia32_xDiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
+ } else if (is_ia32_vfdiv(new_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ }
+ break;
+ default:
+ break;
+ }
+
+ assert(0);
+ return new_rd_Unknown(irg, mode);
+}
+
+static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = NULL;
+ ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
+
+ return res;
+}
+
+static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *call = get_Proj_pred(node);
+ ir_node *new_call = transform_node(env, call);
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *sse_load;
+ const arch_register_class_t *cls;
+
+ /* The following is kinda tricky: If we're using SSE, then we have to
+ * move the result value of the call in floating point registers to an
+ * xmm register, we therefore construct a GetST0 -> xLoad sequence
+ * after the call, we have to make sure to correctly make the
+ * MemProj and the result Proj use these 2 nodes
+ */
+ if (proj == pn_be_Call_M_regular) {
+ // get new node for result, are we doing the sse load/store hack?
+ ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
+ ir_node *call_res_new;
+ ir_node *call_res_pred = NULL;
+
+ if (call_res != NULL) {
+ call_res_new = transform_node(env, call_res);
+ call_res_pred = get_Proj_pred(call_res_new);
+ }
+
+ if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
+ return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
+ } else {
+ assert(is_ia32_xLoad(call_res_pred));
+ return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
+ }
+ }
+ if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env->cg)) {
+ ir_node *fstp;
+ ir_node *frame = get_irg_frame(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *p;
+ ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
+ ir_node *keepin[1];
+ const arch_register_class_t *cls;
+
+ /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
+ call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
+
+ /* store st(0) onto stack */
+ fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
+
+ set_ia32_ls_mode(fstp, mode);
+ set_ia32_op_type(fstp, ia32_AddrModeD);
+ set_ia32_use_frame(fstp);
+ set_ia32_am_flavour(fstp, ia32_am_B);
+ set_ia32_am_support(fstp, ia32_am_Dest);
+
+ /* load into SSE register */
+ sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
+ set_ia32_ls_mode(sse_load, mode);
+ set_ia32_op_type(sse_load, ia32_AddrModeS);
+ set_ia32_use_frame(sse_load);
+ set_ia32_am_flavour(sse_load, ia32_am_B);
+ set_ia32_am_support(sse_load, ia32_am_Source);
+
+ sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
+
+ /* now: create new Keep whith all former ins and one additional in - the result Proj */
+
+ /* get a Proj representing a caller save register */
+ p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
+ assert(is_Proj(p) && "Proj expected.");
+
+ /* user of the the proj is the Keep */
+ p = get_edge_src_irn(get_irn_out_edge_first(p));
+ assert(be_is_Keep(p) && "Keep expected.");
+
+ /* keep the result */
+ cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
+ keepin[0] = sse_load;
+ be_new_Keep(cls, irg, block, 1, keepin);
+
+ return sse_load;
+ }
+
+ /* transform call modes */
+ if (mode_is_data(mode)) {
+ cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
+ mode = cls->mode;
+ }
+
+ return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
+}
+
+static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *pred = get_Proj_pred(node);
+ long proj = get_Proj_proj(node);
+
+ if (is_Store(pred) || be_is_FrameStore(pred)) {
+ if (proj == pn_Store_M) {
+ return transform_node(env, pred);
+ } else {
+ assert(0);
+ return new_r_Bad(irg);
+ }
+ } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
+ return gen_Proj_Load(env, node);
+ } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
+ return gen_Proj_DivMod(env, node);
+ } else if (is_CopyB(pred)) {
+ return gen_Proj_CopyB(env, node);
+ } else if (is_Quot(pred)) {
+ return gen_Proj_Quot(env, node);
+ } else if (is_ia32_l_vfdiv(pred)) {
+ return gen_Proj_l_vfdiv(env, node);
+ } else if (be_is_SubSP(pred)) {
+ return gen_Proj_be_SubSP(env, node);
+ } else if (be_is_AddSP(pred)) {
+ return gen_Proj_be_AddSP(env, node);
+ } else if (be_is_Call(pred)) {
+ return gen_Proj_be_Call(env, node);
+ } else if (get_irn_op(pred) == op_Start) {
+ if (proj == pn_Start_X_initial_exec) {
+ ir_node *block = get_nodes_block(pred);
+ ir_node *jump;
+
+ /* we exchange the ProjX with a jump */
+ block = transform_node(env, block);
+ jump = new_rd_Jmp(dbgi, irg, block);
+ ir_fprintf(stderr, "created jump: %+F\n", jump);
+ return jump;
+ }
+ if (node == env->old_anchors[anchor_tls]) {
+ return gen_Proj_tls(env, node);
+ }
+ } else {
+ ir_node *new_pred = transform_node(env, pred);
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_mode *mode = get_irn_mode(node);
+ if (mode_needs_gp_reg(mode)) {
+ return new_r_Proj(irg, block, new_pred, mode_Iu, get_Proj_proj(node));
+ }
+ }
+
+ return duplicate_node(env, node);
+}
+
+/**
+ * Enters all transform functions into the generic pointer
+ */
+static void register_transformers(void) {
+ ir_op *op_Max, *op_Min, *op_Mulh;
+
+ /* first clear the generic function pointer for all ops */
+ clear_irp_opcodes_generic_func();
+
+#define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
+#define BAD(a) op_##a->ops.generic = (op_func)bad_transform
+
+ GEN(Add);
+ GEN(Sub);
+ GEN(Mul);
+ GEN(And);
+ GEN(Or);
+ GEN(Eor);
+
+ GEN(Shl);
+ GEN(Shr);
+ GEN(Shrs);
+ GEN(Rot);
+
+ GEN(Quot);
+
+ GEN(Div);
+ GEN(Mod);
+ GEN(DivMod);
+
+ GEN(Minus);
+ GEN(Conv);
+ GEN(Abs);
+ GEN(Not);
+
+ GEN(Load);
+ GEN(Store);
+ GEN(Cond);
+
+ GEN(CopyB);
+ //GEN(Mux);
+ BAD(Mux);
+ GEN(Psi);
+ GEN(Proj);
+ GEN(Phi);
+
+ GEN(Block);
+ GEN(End);
+
+ /* transform ops from intrinsic lowering */
+ GEN(ia32_l_Add);
+ GEN(ia32_l_Adc);
+ GEN(ia32_l_Sub);
+ GEN(ia32_l_Sbb);
+ GEN(ia32_l_Neg);
+ GEN(ia32_l_Mul);
+ GEN(ia32_l_Xor);
+ GEN(ia32_l_IMul);
+ GEN(ia32_l_Shl);
+ GEN(ia32_l_Shr);
+ GEN(ia32_l_Sar);
+ GEN(ia32_l_ShlD);
+ GEN(ia32_l_ShrD);
+ GEN(ia32_l_vfdiv);
+ GEN(ia32_l_vfprem);
+ GEN(ia32_l_vfmul);
+ GEN(ia32_l_vfsub);
+ GEN(ia32_l_vfild);
+ GEN(ia32_l_Load);
+ /* GEN(ia32_l_vfist); TODO */
+ GEN(ia32_l_Store);
+ GEN(ia32_l_X87toSSE);
+ GEN(ia32_l_SSEtoX87);
+
+ GEN(Const);
+ GEN(SymConst);
+
+ /* we should never see these nodes */
+ BAD(Raise);
+ BAD(Sel);
+ BAD(InstOf);
+ BAD(Cast);
+ BAD(Free);
+ BAD(Tuple);
+ BAD(Id);
+ //BAD(Bad);
+ BAD(Confirm);
+ BAD(Filter);
+ BAD(CallBegin);
+ BAD(EndReg);
+ BAD(EndExcept);
+
+ /* handle generic backend nodes */
+ GEN(be_FrameAddr);
+ //GEN(be_Call);
+ GEN(be_Return);
+ GEN(be_FrameLoad);
+ GEN(be_FrameStore);
+ GEN(be_StackParam);
+ GEN(be_AddSP);
+ GEN(be_SubSP);
+
+ /* set the register for all Unknown nodes */
+ GEN(Unknown);
+
+ op_Max = get_op_Max();
+ if (op_Max)
+ GEN(Max);
+ op_Min = get_op_Min();
+ if (op_Min)
+ GEN(Min);
+ op_Mulh = get_op_Mulh();
+ if (op_Mulh)
+ GEN(Mulh);
+
+#undef GEN
+#undef BAD
+}
+
+static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
+ ir_node *new_node)
+{
+ int i;
+ int deps = get_irn_deps(old_node);
+
+ for (i = 0; i < deps; ++i) {
+ ir_node *dep = get_irn_dep(old_node, i);
+ ir_node *new_dep = transform_node(env, dep);
+
+ add_irn_dep(new_node, new_dep);
+ }
+}
+
+static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
+{
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_graph *irg = env->irg;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_op *op = get_irn_op(node);
+ ir_node *new_node;
+ int i, arity;
+
+ arity = get_irn_arity(node);
+ if (op->opar == oparity_dynamic) {
+ new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ in = transform_node(env, in);
+ add_irn_n(new_node, in);
+ }
+ } else {
+ ir_node **ins = alloca(arity * sizeof(ins[0]));
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ ins[i] = transform_node(env, in);
+ }
+
+ new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
+ }
+
+ copy_node_attr(node, new_node);
+ duplicate_deps(env, node, new_node);
+
+#ifdef DEBUG_libfirm
+ new_node->node_nr = node->node_nr;
+#endif
+
+ return new_node;
+}
+
+/**
+ * Calls transformation function for given node and marks it visited.
+ */
+static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) {
+ ir_node *new_node;
+ ir_op *op = get_irn_op(node);
+
+ if (irn_visited(node)) {
+ assert(get_new_node(node) != NULL);
+ return get_new_node(node);
+ }
+
+ mark_irn_visited(node);
+ DEBUG_ONLY(set_new_node(node, NULL));
+
+ if (op->ops.generic) {
+ transform_func *transform = (transform_func *)op->ops.generic;
+
+ new_node = (*transform)(env, node);
+ assert(new_node != NULL);
+ } else {
+ new_node = duplicate_node(env, node);
+ }
+ DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
+
+ set_new_node(node, new_node);
+ mark_irn_visited(new_node);
+ hook_dead_node_elim_subst(current_ir_graph, node, new_node);
+ return new_node;
+}
+
+/**
+ * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
+ */
+static void fix_loops(ia32_transform_env_t *env, ir_node *node) {
+ int i, arity;
+
+ if (irn_visited(node))
+ return;
+
+ mark_irn_visited(node);
+
+ assert(node_is_in_irgs_storage(env->irg, node));
+
+ if (! is_Block(node)) {
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = (ir_node *)get_irn_link(block);
+
+ if (new_block != NULL) {
+ set_nodes_block(node, new_block);
+ block = new_block;
+ }
+
+ fix_loops(env, block);
+ }
+
+ arity = get_irn_arity(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ ir_node *nw = (ir_node *)get_irn_link(in);
+
+ if (nw != NULL && nw != in) {
+ set_irn_n(node, i, nw);
+ in = nw;
+ }
+
+ fix_loops(env, in);
+ }
+
+ arity = get_irn_deps(node);
+ for (i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_dep(node, i);
+ ir_node *nw = (ir_node *)get_irn_link(in);
+
+ if (nw != NULL && nw != in) {
+ set_irn_dep(node, i, nw);
+ in = nw;
+ }
+
+ fix_loops(env, in);
+ }
+}
+
+static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
+{
+ if (*place == NULL)
+ return;
+
+ *place = transform_node(env, *place);
+}
+
+/**
+ * Transforms all nodes. Deletes the old obstack and creates a new one.
+ */
+static void transform_nodes(ia32_code_gen_t *cg) {
+ int i;
+ ir_graph *irg = cg->irg;
+ ir_node *old_end;
+ ia32_transform_env_t env;
+
+ hook_dead_node_elim(irg, 1);
+
+ inc_irg_visited(irg);
+
+ env.irg = irg;
+ env.cg = cg;
+ env.visited = get_irg_visited(irg);
+ env.worklist = new_pdeq();
+ env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
+
+ old_end = get_irg_end(irg);
+
+ /* put all anchor nodes in the worklist */
+ for (i = 0; i < anchor_max; ++i) {
+ ir_node *anchor = irg->anchors[i];
+
+ if (anchor == NULL)
+ continue;
+ pdeq_putr(env.worklist, anchor);
+
+ /* remember anchor */
+ env.old_anchors[i] = anchor;
+ /* and set it to NULL to make sure we don't accidently use it */
+ irg->anchors[i] = NULL;
+ }
+
+ /* pre transform some anchors (so they are available in the other transform
+ * functions) */
+ set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
+ set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
+ set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
+ set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
+ set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
+
+ pre_transform_node(&cg->unknown_gp, &env);
+ pre_transform_node(&cg->unknown_vfp, &env);
+ pre_transform_node(&cg->unknown_xmm, &env);
+ pre_transform_node(&cg->noreg_gp, &env);
+ pre_transform_node(&cg->noreg_vfp, &env);
+ pre_transform_node(&cg->noreg_xmm, &env);
+
+ /* process worklist (this should transform all nodes in the graph) */
+ while (! pdeq_empty(env.worklist)) {
+ ir_node *node = pdeq_getl(env.worklist);
+ transform_node(&env, node);
+ }
+
+ /* fix loops and set new anchors*/
+ inc_irg_visited(irg);
+ for (i = 0; i < anchor_max; ++i) {
+ ir_node *anchor = env.old_anchors[i];
+
+ if (anchor == NULL)
+ continue;
+
+ anchor = get_irn_link(anchor);
+ fix_loops(&env, anchor);
+ assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
+ irg->anchors[i] = anchor;
+ }
+
+ del_pdeq(env.worklist);
+ free_End(old_end);
+ hook_dead_node_elim(irg, 0);
+}
+
+void ia32_transform_graph(ia32_code_gen_t *cg)
+{
+ ir_graph *irg = cg->irg;
+ be_irg_t *birg = cg->birg;
+ ir_graph *old_current_ir_graph = current_ir_graph;
+ int old_interprocedural_view = get_interprocedural_view();
+ struct obstack *old_obst = NULL;
+ struct obstack *new_obst = NULL;
+
+ current_ir_graph = irg;
+ set_interprocedural_view(0);
+ register_transformers();
+
+ /* most analysis info is wrong after transformation */
+ free_callee_info(irg);
+ free_irg_outs(irg);
+ irg->outs_state = outs_none;
+ free_trouts();
+ free_loop_information(irg);
+ set_irg_doms_inconsistent(irg);
+ be_invalidate_liveness(birg);
+ be_invalidate_dom_front(birg);
+
+ /* create a new obstack */
+ old_obst = irg->obst;
+ new_obst = xmalloc(sizeof(*new_obst));
+ obstack_init(new_obst);
+ irg->obst = new_obst;
+ irg->last_node_idx = 0;
+
+ /* create new value table for CSE */
+ del_identities(irg->value_table);
+ irg->value_table = new_identities();
+
+ /* do the main transformation */
+ transform_nodes(cg);
+
+ /* we don't want the globals anchor anymore */
+ set_irg_globals(irg, new_r_Bad(irg));
+
+ /* free the old obstack */
+ obstack_free(old_obst, 0);
+ xfree(old_obst);
+
+ /* restore state */
+ current_ir_graph = old_current_ir_graph;
+ set_interprocedural_view(old_interprocedural_view);
+
+ /* recalculate edges */
+ edges_deactivate(irg);
+ edges_activate(irg);
+}
+
+/**
+ * Transforms a psi condition.
+ */
+static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
+ int i;
+
+ /* if the mode is target mode, we have already seen this part of the tree */
+ if (get_irn_mode(cond) == mode)
+ return;
+
+ assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
+
+ set_irn_mode(cond, mode);
+
+ for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
+ ir_node *in = get_irn_n(cond, i);
+
+ /* if in is a compare: transform into Set/xCmp */
+ if (is_Proj(in)) {
+ ir_node *new_op = NULL;
+ ir_node *cmp = get_Proj_pred(in);
+ ir_node *cmp_a = get_Cmp_left(cmp);
+ ir_node *cmp_b = get_Cmp_right(cmp);
+ dbg_info *dbgi = get_irn_dbg_info(cmp);
+ ir_graph *irg = get_irn_irg(cmp);
+ ir_node *block = get_nodes_block(cmp);
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ int pnc = get_Proj_proj(in);
+
+ /* this is a compare */
+ if (mode_is_float(mode)) {
+ /* Psi is float, we need a floating point compare */
+
+ if (USE_SSE2(cg)) {
+ ir_mode *m = get_irn_mode(cmp_a);
+ /* SSE FPU */
+ if (! mode_is_float(m)) {
+ cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
+ cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
+ } else if (m == mode_F) {
+ /* we convert cmp values always to double, to get correct bitmask with cmpsd */
+ cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
+ cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
+ }
+
+ new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
+ set_ia32_pncode(new_op, pnc);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
+ } else {
+ /* x87 FPU */
+ assert(0);
+ }
+ } else {
+ /* integer Psi */
+ construct_binop_func *set_func = NULL;
+
+ if (mode_is_float(get_irn_mode(cmp_a))) {
+ /* 1st case: compare operands are floats */
+ FP_USED(cg);
+
+ if (USE_SSE2(cg)) {
+ /* SSE FPU */
+ set_func = new_rd_ia32_xCmpSet;
+ } else {
+ /* x87 FPU */
+ set_func = new_rd_ia32_vfCmpSet;
+ }
+
+ pnc &= 7; /* fp compare -> int compare */
+ } else {
+ /* 2nd case: compare operand are integer too */
+ set_func = new_rd_ia32_CmpSet;
+ }
+
+ new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
+ if (! mode_is_signed(mode))
+ pnc |= ia32_pn_Cmp_Unsigned;
+
+ set_ia32_pncode(new_op, pnc);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ }
+
+ /* the the new compare as in */
+ set_irn_n(cond, i, new_op);
+ } else {
+ /* another complex condition */
+ transform_psi_cond(in, mode, cg);
+ }
+ }
+}
+
+/**
+ * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
+ * We create a Set node, respectively a xCmp in case the Psi is a float, for
+ * each compare, which causes the compare result to be stored in a register. The
+ * "And"s and "Or"s are transformed later, we just have to set their mode right.
+ */
+void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
+ ia32_code_gen_t *cg = env;
+ ir_node *psi_sel, *new_cmp, *block;
+ ir_graph *irg;
+ ir_mode *mode;
+
+ /* check for Psi */
+ if (get_irn_opcode(node) != iro_Psi)
+ return;
+
+ psi_sel = get_Psi_cond(node, 0);
+
+ /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
+ if (is_Proj(psi_sel)) {
+ assert(is_Cmp(get_Proj_pred(psi_sel)));
+ return;
+ }
+
+ //mode = get_irn_mode(node);
+ // TODO probably wrong...
+ mode = mode_Iu;
+
+ transform_psi_cond(psi_sel, mode, cg);
+
+ irg = get_irn_irg(node);
+ block = get_nodes_block(node);
+
+ /* we need to compare the evaluated condition tree with 0 */
+ mode = get_irn_mode(node);
+ if (mode_is_float(mode)) {
+ /* BEWARE: new_r_Const_long works for floating point as well */
+ ir_node *zero = new_r_Const_long(irg, block, mode, 0);
+
+ psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
+ new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
+ new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
+ } else {
+ ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
+ new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
+ new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
+ }
+
+ set_Psi_cond(node, 0, new_cmp);
+}
+
+void ia32_init_transform(void)
+{
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");