+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
+ "outs" => [ "DST", "SRC", "M" ],
+},
+
+# Conversions
+
+"Conv_I2I" => {
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
+ "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Int -> Int",
+ "outs" => [ "res", "M" ],
+},
+
+"Conv_I2I8Bit" => {
+ "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
+ "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Int -> Int",
+ "outs" => [ "res", "M" ],
+},
+
+"Conv_I2FP" => {
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
+ "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Int -> Floating Point",
+ "outs" => [ "res", "M" ],
+ "latency" => 10,
+},
+
+"Conv_FP2I" => {
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
+ "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Floating Point -> Int",
+ "outs" => [ "res", "M" ],
+ "latency" => 10,
+},
+
+"Conv_FP2FP" => {
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
+ "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Floating Point -> Floating Point",
+ "outs" => [ "res", "M" ],
+ "latency" => 8,
+},
+
+"CmpCMov" => {
+ "irn_flags" => "R",
+ "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
+ "latency" => 2,
+},
+
+"PsiCondCMov" => {
+ "irn_flags" => "R",
+ "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
+ "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
+ "latency" => 2,
+},
+
+"xCmpCMov" => {
+ "irn_flags" => "R",
+ "comment" => "construct Conditional Move: SSE Compare + int CMov ",
+ "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
+ "latency" => 5,
+},
+
+"vfCmpCMov" => {
+ "irn_flags" => "R",
+ "comment" => "construct Conditional Move: x87 Compare + int CMov",
+ "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
+ "latency" => 10,
+},
+
+"CmpSet" => {
+ "irn_flags" => "R",
+ "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 2,
+},
+
+"PsiCondSet" => {
+ "irn_flags" => "R",
+ "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
+ "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
+ "latency" => 2,
+},
+
+"xCmpSet" => {
+ "irn_flags" => "R",
+ "comment" => "construct Set: SSE Compare + int Set",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 5,
+},
+
+"vfCmpSet" => {
+ "irn_flags" => "R",
+ "comment" => "construct Set: x87 Compare + int Set",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 10,
+},
+
+"vfCMov" => {
+ "irn_flags" => "R",
+ "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
+ "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
+ "latency" => 10,
+},
+
+#----------------------------------------------------------#
+# _ _ _ __ _ _ #
+# (_) | | | | / _| | | | #
+# __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
+# \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
+# \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
+# \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
+# | | #
+# _ __ ___ __| | ___ ___ #
+# | '_ \ / _ \ / _` |/ _ \/ __| #
+# | | | | (_) | (_| | __/\__ \ #
+# |_| |_|\___/ \__,_|\___||___/ #
+#----------------------------------------------------------#
+
+"vfadd" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 4,
+},
+
+"vfmul" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 4,
+},
+
+"l_vfmul" => {
+ "op_flags" => "C",
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "arity" => 2,
+},
+
+"vfsub" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Sub: Sub(a, b) = a - b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 4,
+},
+
+"l_vfsub" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
+ "arity" => 2,
+},
+
+"vfdiv" => {
+ "comment" => "virtual fp Div: Div(a, b) = a / b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 20,
+},
+
+"l_vfdiv" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
+ "arity" => 2,
+},
+
+"vfabs" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Abs: Abs(a) = |a|",
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+ "latency" => 2,
+},
+
+"vfchs" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Chs: Chs(a) = -a",
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+ "latency" => 2,
+},
+
+"vfsin" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Sin: Sin(a) = sin(a)",
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+ "latency" => 150,
+},
+
+"vfcos" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Cos: Cos(a) = cos(a)",
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+ "latency" => 150,
+},
+
+"vfsqrt" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+ "latency" => 30,
+},
+
+# virtual Load and Store
+
+"vfld" => {
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 2,
+},
+
+"vfst" => {
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
+ "outs" => [ "M" ],
+ "latency" => 2,
+},
+
+# Conversions
+
+"vfild" => {
+ "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+ "outs" => [ "res", "M" ],
+ "latency" => 4,
+},
+
+"l_vfild" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
+ "outs" => [ "res", "M" ],
+ "arity" => 2,
+},
+
+"vfist" => {
+ "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
+ "outs" => [ "M" ],
+ "latency" => 4,
+},
+
+"l_vfist" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "outs" => [ "M" ],
+ "arity" => 3,
+},
+
+
+# constants
+
+"vfldz" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfld1" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfldpi" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load pi: Ld pi -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfldln2" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfldlg2" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfldl2t" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfldl2e" => {
+ "irn_flags" => "R",
+ "comment" => "virtual fp Load ld e: Ld ld e -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 4,
+},
+
+"vfConst" => {
+ "op_flags" => "c",
+ "irn_flags" => "R",
+ "init_attr" => " set_ia32_ls_mode(res, mode);",
+ "comment" => "represents a virtual floating point constant",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "latency" => 3,
+},
+
+# other
+
+"vfCondJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "represents a virtual floating point compare",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
+ "outs" => [ "false", "true", "temp_reg_eax" ],
+ "latency" => 10,
+},
+
+#------------------------------------------------------------------------#
+# ___ _____ __ _ _ _ #
+# __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
+# \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
+# > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
+# /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
+#------------------------------------------------------------------------#
+
+"fadd" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
+ "reg_req" => { },
+ "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
+},
+
+"faddp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
+ "reg_req" => { },
+ "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
+},
+
+"fmul" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
+ "reg_req" => { },
+ "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
+},
+
+"fmulp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
+ "reg_req" => { },
+ "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
+},
+
+"fsub" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Sub: Sub(a, b) = a - b",
+ "reg_req" => { },
+ "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
+},
+
+"fsubp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Sub: Sub(a, b) = a - b",
+ "reg_req" => { },
+ "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
+},
+
+"fsubr" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "irn_flags" => "R",
+ "comment" => "x87 fp SubR: SubR(a, b) = b - a",
+ "reg_req" => { },
+ "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
+},
+
+"fsubrp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "irn_flags" => "R",
+ "comment" => "x87 fp SubR: SubR(a, b) = b - a",
+ "reg_req" => { },
+ "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
+},
+
+"fdiv" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Div: Div(a, b) = a / b",
+ "reg_req" => { },
+ "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
+},
+
+"fdivp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Div: Div(a, b) = a / b",
+ "reg_req" => { },
+ "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
+},
+
+"fdivr" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp DivR: DivR(a, b) = b / a",
+ "reg_req" => { },
+ "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
+},
+
+"fdivrp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp DivR: DivR(a, b) = b / a",
+ "reg_req" => { },
+ "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
+},
+
+"fabs" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Abs: Abs(a) = |a|",
+ "reg_req" => { },
+ "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
+},
+
+"fchs" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Chs: Chs(a) = -a",
+ "reg_req" => { },
+ "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
+},
+
+"fsin" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Sin: Sin(a) = sin(a)",
+ "reg_req" => { },
+ "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
+},
+
+"fcos" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Cos: Cos(a) = cos(a)",
+ "reg_req" => { },
+ "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
+},
+
+"fsqrt" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
+ "reg_req" => { },
+ "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
+},
+
+# x87 Load and Store
+
+"fld" => {
+ "rd_constructor" => "NONE",
+ "op_flags" => "R|L|F",
+ "state" => "exc_pinned",
+ "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
+ "reg_req" => { },
+ "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
+},
+
+"fst" => {
+ "rd_constructor" => "NONE",
+ "op_flags" => "R|L|F",
+ "state" => "exc_pinned",
+ "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
+},
+
+"fstp" => {
+ "rd_constructor" => "NONE",
+ "op_flags" => "R|L|F",
+ "state" => "exc_pinned",
+ "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
+},
+
+# Conversions
+
+"fild" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
+ "reg_req" => { },
+ "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
+},
+
+"fist" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
+},
+
+"fistp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
+},
+
+# constants
+
+"fldz" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fldz /* x87 0.0 -> %D1 */',
+},
+
+"fld1" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fld1 /* x87 1.0 -> %D1 */',
+},
+
+"fldpi" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load pi: Ld pi -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fldpi /* x87 pi -> %D1 */',
+},
+
+"fldln2" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
+},
+
+"fldlg2" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
+},
+
+"fldl2t" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
+},
+
+"fldl2e" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "comment" => "x87 fp Load ld e: Ld ld e -> reg",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
+},
+
+"fldConst" => {
+ "op_flags" => "R|c",
+ "irn_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "represents a x87 constant",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "out" => [ "vfp" ] },
+ "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
+},
+
+# fxch, fpush, fpop
+# Note that it is NEVER allowed to do CSE on these nodes
+# Moreover, note the virtual register requierements!
+
+"fxch" => {
+ "op_flags" => "R|K",
+ "comment" => "x87 stack exchange",
+ "reg_req" => { },
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
+},
+
+"fpush" => {
+ "op_flags" => "R|K",
+ "comment" => "x87 stack push",
+ "reg_req" => {},
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fld %X1 /* x87 push %X1 */',
+},
+
+"fpushCopy" => {
+ "op_flags" => "R",
+ "comment" => "x87 stack push",
+ "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fld %X1 /* x87 push %X1 */',
+},
+
+"fpop" => {
+ "op_flags" => "R|K",
+ "comment" => "x87 stack pop",
+ "reg_req" => { },
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fstp %X1 /* x87 pop %X1 */',
+},
+
+# compare
+
+"fcomJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcompJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare and pop",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomppJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare and pop twice",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomrJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare reverse",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomrpJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare reverse and pop",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { },
+},
+
+"fcomrppJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "floating point compare reverse and pop twice",