+#-----------------------------------------------------------------#
+# _ _ _ #
+# (_) | | | | #
+# _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
+# | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
+# | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
+# |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
+# __/ | #
+# |___/ #
+#-----------------------------------------------------------------#
+
+# commutative operations
+
+# NOTE:
+# All nodes supporting Addressmode have 5 INs:
+# 1 - base r1 == NoReg in case of no AM or no base
+# 2 - index r2 == NoReg in case of no AM or no index
+# 3 - op1 r3 == always present
+# 4 - op2 r4 == NoReg in case of immediate operation
+# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
+
+Add => {
+ irn_flags => "R",
+ comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. addl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Adc => {
+ comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. adcl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Add64Bit => {
+ irn_flags => "R",
+ comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
+ arity => 4,
+ reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
+ emit => '
+. movl %S1, %D1
+. movl %S2, %D2
+. addl %S3, %D1
+. adcl %S4, %D2
+',
+ outs => [ "low_res", "high_res" ],
+ units => [ "GP" ],
+},
+
+l_Add => {
+ op_flags => "C",
+ irn_flags => "R",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
+ arity => 2,
+},
+
+l_Adc => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
+ arity => 2,
+},
+
+Mul => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
+ comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
+ reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ emit => '. mull %unop',
+ outs => [ "EAX", "EDX", "M" ],
+ latency => 10,
+ units => [ "GP" ],
+},
+
+l_Mul => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
+ outs => [ "EAX", "EDX", "M" ],
+ arity => 2
+},
+
+IMul => {
+ irn_flags => "R",
+ comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. imull %binop',
+ latency => 5,
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+IMul1OP => {
+ irn_flags => "R",
+ comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
+ reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ emit => '. imull %unop',
+ outs => [ "EAX", "EDX", "M" ],
+ latency => 5,
+ units => [ "GP" ],
+},
+
+l_IMul => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
+ arity => 2
+},
+
+And => {
+ irn_flags => "R",
+ comment => "construct And: And(a, b) = And(b, a) = a AND b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. andl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Or => {
+ irn_flags => "R",
+ comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. orl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Xor => {
+ irn_flags => "R",
+ comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. xorl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_Xor => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
+ arity => 2
+},
+
+# not commutative operations
+
+Sub => {
+ irn_flags => "R",
+ comment => "construct Sub: Sub(a, b) = a - b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. subl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Sbb => {
+ comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
+ emit => '. sbbl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Sub64Bit => {
+ irn_flags => "R",
+ comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
+ arity => 4,
+ reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
+ emit => '
+. movl %S1, %D1
+. movl %S2, %D2
+. subl %S3, %D1
+. sbbl %S4, %D2
+',
+ outs => [ "low_res", "high_res" ],
+ units => [ "GP" ],
+},
+
+l_Sub => {
+ irn_flags => "R",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Sub: Sub(a, b) = a - b",
+ arity => 2,
+},
+
+l_Sbb => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
+ arity => 2,
+},
+
+IDiv => {
+ op_flags => "F|L",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ attr => "ia32_op_flavour_t dm_flav",
+ init_attr => "attr->data.op_flav = dm_flav;",
+ emit => ". idivl %unop",
+ outs => [ "div_res", "mod_res", "M" ],
+ latency => 25,
+ units => [ "GP" ],
+},
+
+Div => {
+ op_flags => "F|L",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ attr => "ia32_op_flavour_t dm_flav",
+ init_attr => "attr->data.op_flav = dm_flav;",
+ emit => ". divl %unop",
+ outs => [ "div_res", "mod_res", "M" ],
+ latency => 25,
+ units => [ "GP" ],
+},
+
+Shl => {
+ irn_flags => "R",
+ comment => "construct Shl: Shl(a, b) = a << b",
+ reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
+ emit => '. shll %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_Shl => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered Shl: Shl(a, b) = a << b",
+ arity => 2
+},
+
+ShlD => {
+ irn_flags => "R",
+ comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
+ # Out requirements is: different from all in
+ # This is because, out must be different from LowPart and ShiftCount.
+ # We could say "!ecx !in_r4" but it can occur, that all values live through
+ # this Shift and the only value dying is the ShiftCount. Then there would be a
+ # register missing, as result must not be ecx and all other registers are
+ # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+ # (and probably never will). So we create artificial interferences of the result
+ # with all inputs, so the spiller can always assure a free register.
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+ emit =>
+'
+if (get_ia32_immop_type(node) == ia32_ImmNone) {
+ if (get_ia32_op_type(node) == ia32_AddrModeD) {
+ . shldl %%cl, %S4, %AM
+ } else {
+ . shldl %%cl, %S4, %S3
+ }
+} else {
+ if (get_ia32_op_type(node) == ia32_AddrModeD) {
+ . shldl $%C, %S4, %AM
+ } else {
+ . shldl $%C, %S4, %S3
+ }
+}
+',
+ latency => 6,
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_ShlD => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
+ arity => 3,
+},
+
+Shr => {
+ irn_flags => "R",
+ comment => "construct Shr: Shr(a, b) = a >> b",
+ reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
+ emit => '. shrl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_Shr => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered Shr: Shr(a, b) = a << b",
+ arity => 2
+},
+
+ShrD => {
+ irn_flags => "R",
+ comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
+ # Out requirements is: different from all in
+ # This is because, out must be different from LowPart and ShiftCount.
+ # We could say "!ecx !in_r4" but it can occur, that all values live through
+ # this Shift and the only value dying is the ShiftCount. Then there would be a
+ # register missing, as result must not be ecx and all other registers are
+ # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+ # (and probably never will). So we create artificial interferences of the result
+ # with all inputs, so the spiller can always assure a free register.
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+ emit => '
+if (get_ia32_immop_type(node) == ia32_ImmNone) {
+ if (get_ia32_op_type(node) == ia32_AddrModeD) {
+ . shrdl %%cl, %S4, %AM
+ } else {
+ . shrdl %%cl, %S4, %S3
+ }
+} else {
+ if (get_ia32_op_type(node) == ia32_AddrModeD) {
+ . shrdl $%C, %S4, %AM
+ } else {
+ . shrdl $%C, %S4, %S3
+ }
+}
+',
+ latency => 6,
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_ShrD => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
+ arity => 3
+},
+
+Sar => {
+ irn_flags => "R",
+ comment => "construct Shrs: Shrs(a, b) = a >> b",
+ reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
+ emit => '. sarl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_Sar => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered Sar: Sar(a, b) = a << b",
+ arity => 2
+},
+
+Ror => {
+ irn_flags => "R",
+ comment => "construct Ror: Ror(a, b) = a ROR b",
+ reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
+ emit => '. rorl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Rol => {
+ irn_flags => "R",
+ comment => "construct Rol: Rol(a, b) = a ROL b",
+ reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
+ emit => '. roll %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+# unary operations
+
+Neg => {
+ irn_flags => "R",
+ comment => "construct Minus: Minus(a) = -a",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. negl %unop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Minus64Bit => {
+ irn_flags => "R",
+ comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
+ arity => 4,
+ reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
+ emit => '
+. movl %S1, %D1
+. movl %S1, %D2
+. subl %S2, %D1
+. sbbl %S3, %D2
+',
+ outs => [ "low_res", "high_res" ],
+ units => [ "GP" ],
+},
+
+
+l_Neg => {
+ cmp_attr => "return 1;",
+ comment => "construct lowered Minus: Minus(a) = -a",
+ arity => 1,
+},
+
+Inc => {
+ irn_flags => "R",
+ comment => "construct Increment: Inc(a) = a++",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. incl %unop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Dec => {
+ irn_flags => "R",
+ comment => "construct Decrement: Dec(a) = a--",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. decl %unop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Not => {
+ irn_flags => "R",
+ comment => "construct Not: Not(a) = !a",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. notl %unop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+# other operations
+
+CondJmp => {
+ op_flags => "L|X|Y",
+ comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
+ outs => [ "false", "true" ],
+ latency => 3,
+ units => [ "BRANCH" ],
+},
+
+TestJmp => {
+ op_flags => "L|X|Y",
+ comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
+ reg_req => { in => [ "gp", "gp" ] },
+ outs => [ "false", "true" ],
+ latency => 3,
+ units => [ "BRANCH" ],
+},
+
+CJmpAM => {
+ op_flags => "L|X|Y",
+ comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
+ outs => [ "false", "true" ],
+ units => [ "BRANCH" ],
+},
+
+CJmp => {
+ op_flags => "L|X|Y",
+ comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
+ reg_req => { in => [ "gp", "gp" ] },
+ units => [ "BRANCH" ],
+},
+
+SwitchJmp => {
+ op_flags => "L|X|Y",
+ comment => "construct switch",
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
+ latency => 3,
+ units => [ "BRANCH" ],
+},
+
+Const => {
+ op_flags => "c",
+ irn_flags => "R",
+ comment => "represents an integer constant",
+ reg_req => { out => [ "gp" ] },
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Unknown_GP => {
+ op_flags => "c",
+ irn_flags => "I",
+ comment => "unknown value",
+ reg_req => { out => [ "gp_UKNWN" ] },
+ units => [],
+ emit => "",
+ mode => "mode_Iu"
+},
+
+Unknown_VFP => {
+ op_flags => "c",
+ irn_flags => "I",
+ comment => "unknown value",
+ reg_req => { out => [ "vfp_UKNWN" ] },
+ units => [],
+ emit => "",
+ mode => "mode_E"
+},
+
+Unknown_XMM => {
+ op_flags => "c",
+ irn_flags => "I",
+ comment => "unknown value",
+ reg_req => { out => [ "xmm_UKNWN" ] },
+ units => [],
+ emit => "",
+ mode => "mode_E"
+},
+
+NoReg_GP => {
+ op_flags => "c",
+ irn_flags => "I",
+ comment => "unknown GP value",
+ reg_req => { out => [ "gp_NOREG" ] },
+ units => [],
+ emit => "",
+ mode => "mode_Iu"
+},
+
+NoReg_VFP => {
+ op_flags => "c",
+ irn_flags => "I",
+ comment => "unknown VFP value",
+ reg_req => { out => [ "vfp_NOREG" ] },
+ units => [],
+ emit => "",
+ mode => "mode_E"
+},
+
+NoReg_XMM => {
+ op_flags => "c",
+ irn_flags => "I",
+ comment => "unknown XMM value",
+ reg_req => { out => [ "xmm_NOREG" ] },
+ units => [],
+ emit => "",
+ mode => "mode_E"
+},
+
+ChangeCW => {
+ irn_flags => "R",
+ comment => "change floating point control word",
+ reg_req => { out => [ "fp_cw" ] },
+ mode => "mode_Hu",
+ latency => 3,
+ units => [ "GP" ],
+},
+
+FldCW => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
+ latency => 5,
+ emit => ". fldcw %AM",
+ mode => "mode_Hu",
+ units => [ "GP" ],
+},
+
+FstCW => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
+ reg_req => { in => [ "gp", "gp", "fp_cw", "none" ] },
+ latency => 5,
+ emit => ". fstcw %AM",
+ mode => "mode_M",
+ units => [ "GP" ],
+},
+
+Cltd => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
+ comment => "construct CDQ: sign extend EAX -> EDX:EAX",
+ reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
+ emit => '. cltd',
+ outs => [ "EAX", "EDX" ],
+ units => [ "GP" ],
+},
+
+# Load / Store
+
+Load => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
+ latency => 3,
+ emit => ". mov%SE%ME%.l %AM, %D1",
+ outs => [ "res", "M" ],
+ units => [ "GP" ],
+},
+
+l_Load => {
+ op_flags => "L|F",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
+ outs => [ "res", "M" ],
+ arity => 2,
+},
+
+l_Store => {
+ op_flags => "L|F",
+ cmp_attr => "return 1;",
+ state => "exc_pinned",
+ comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
+ arity => 3,
+ mode => "mode_M",
+},
+
+Store => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ emit => '. mov%M %binop',
+ latency => 3,
+ units => [ "GP" ],
+ mode => "mode_M",
+},
+
+Store8Bit => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
+ emit => '. mov%M %binop',
+ latency => 3,
+ units => [ "GP" ],
+ mode => "mode_M",
+},
+
+Lea => {
+ irn_flags => "R",
+ comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
+ reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
+ emit => '. leal %AM, %D1',
+ latency => 2,
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Push => {
+ comment => "push on the stack",
+ reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
+ emit => '. pushl %unop',
+ outs => [ "stack:I|S", "M" ],
+ latency => 3,
+ units => [ "GP" ],
+},
+
+Pop => {
+ comment => "pop a gp register from the stack",
+ reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
+ emit => '. popl %unop',
+ outs => [ "stack:I|S", "res", "M" ],
+ latency => 4,
+ units => [ "GP" ],
+},
+
+Enter => {
+ comment => "create stack frame",
+ reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
+ emit => '. enter',
+ outs => [ "frame:I", "stack:I|S", "M" ],
+ latency => 15,
+ units => [ "GP" ],
+},
+
+Leave => {
+ comment => "destroy stack frame",
+ reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
+ emit => '. leave',
+ outs => [ "frame:I", "stack:I|S" ],
+ latency => 3,
+ units => [ "GP" ],
+},
+
+AddSP => {
+ irn_flags => "I",
+ comment => "allocate space on stack",
+ reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ emit => '. addl %binop',
+ outs => [ "stack:S", "M" ],
+ units => [ "GP" ],
+},
+
+SubSP => {
+ irn_flags => "I",
+ comment => "free space on stack",
+ reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ emit => '. subl %binop',
+ outs => [ "stack:S", "M" ],
+ units => [ "GP" ],
+},
+
+LdTls => {
+ irn_flags => "R",
+ comment => "get the TLS base address",
+ reg_req => { out => [ "gp" ] },
+ units => [ "GP" ],
+},
+
+
+
+#-----------------------------------------------------------------------------#
+# _____ _____ ______ __ _ _ _ #
+# / ____/ ____| ____| / _| | | | | | #
+# | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
+# \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
+# ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
+# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
+#-----------------------------------------------------------------------------#