+"fdiv" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Div: Div(a, b) = a / b",
+ "reg_req" => { },
+ "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+},
+
+"fdivp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Div: Div(a, b) = a / b",
+ "reg_req" => { },
+ "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+},
+
+"fdivr" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp DivR: DivR(a, b) = b / a",
+ "reg_req" => { },
+ "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+},
+
+"fdivrp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp DivR: DivR(a, b) = b / a",
+ "reg_req" => { },
+ "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+},
+
+"fabs" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Abs: Abs(a) = |a|",
+ "reg_req" => { },
+ "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */'
+},
+
+"fchs" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Chs: Chs(a) = -a",
+ "reg_req" => { },
+ "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */'
+},
+
+"fsin" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Sin: Sin(a) = sin(a)",
+ "reg_req" => { },
+ "emit" => '. fsin /* x87 sin(%S1) -> %D1 */'
+},
+
+"fcos" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Cos: Cos(a) = cos(a)",
+ "reg_req" => { },
+ "emit" => '. fcos /* x87 cos(%S1) -> %D1 */'
+},
+
+"fsqrt" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
+ "reg_req" => { },
+ "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */'
+},
+
+# x87 Load and Store
+
+"fld" => {
+ "rd_constructor" => "NONE",
+ "op_flags" => "R|L|F",
+ "state" => "exc_pinned",
+ "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
+ "reg_req" => { },
+ "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */'
+},
+
+"fst" => {
+ "rd_constructor" => "NONE",
+ "op_flags" => "R|L|F",
+ "state" => "exc_pinned",
+ "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */'
+},
+
+"fstp" => {
+ "rd_constructor" => "NONE",
+ "op_flags" => "R|L|F",
+ "state" => "exc_pinned",
+ "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */'
+},
+
+# Conversions
+
+"fild" => {
+ "op_flags" => "R",
+ "irn_flags" => "R",
+ "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
+ "reg_req" => { },
+ "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */'
+},
+
+"fist" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fist %ia32_emit_binop /* integer Store(%A3) -> (%A1) */'
+},
+
+"fistp" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "reg_req" => { },
+ "emit" => '. fistp %ia32_emit_binop /* integer Store(%A3) -> (%A1) and pop */'
+},
+
+# constants
+
+"fldz" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
+ "reg_req" => { },
+ "emit" => '. fldz /* x87 0.0 -> %D1 */'
+},
+
+"fld1" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
+ "reg_req" => { },
+ "emit" => '. fld1 /* x87 1.0 -> %D1 */'
+},
+
+"fldpi" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load pi: Ld pi -> reg",
+ "reg_req" => { },
+ "emit" => '. fldpi /* x87 pi -> %D1 */'
+},
+
+"fldln2" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
+ "reg_req" => { },
+ "emit" => '. fldln2 /* x87 ln(2) -> %D1 */'
+},
+
+"fldlg2" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
+ "reg_req" => { },
+ "emit" => '. fldlg2 /* x87 log(2) -> %D1 */'
+},
+
+"fldl2t" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
+ "reg_req" => { },
+ "emit" => '. fldll2t /* x87 ld(10) -> %D1 */'
+},
+
+"fldl2e" => {
+ "op_flags" => "R",
+ "rd_constructor" => "NONE",
+ "comment" => "x87 fp Load ld e: Ld ld e -> reg",
+ "reg_req" => { },
+ "emit" => '. fldl2e /* x87 ld(e) -> %D1 */'
+},
+
+"fldConst" => {
+ "op_flags" => "R",
+ "op_flags" => "c",
+ "irn_flags" => "R",
+ "comment" => "represents a x87 constant",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "out" => [ "st" ] },
+ "emit" => '. fld%M %C /* Load fConst into register -> %D1 */',
+},
+
+# fxch, fpush
+# Note that it is NEVER allowed to do CSE on these nodes
+
+"fxch" => {
+ "op_flags" => "R|K",
+ "comment" => "x87 stack exchange",
+ "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
+},
+
+"fpush" => {
+ "op_flags" => "R",
+ "comment" => "x87 stack push",
+ "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
+ "cmp_attr" => " return 1;\n",
+ "emit" => '. fld %X1 /* x87 push %X1 */',
+},