+"Store" => {
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+},
+
+"Store8Bit" => {
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+},
+
+"Lea" => {
+ "irn_flags" => "R",
+ "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+ "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
+},
+
+#-----------------------------------------------------------------------------#
+# _____ _____ ______ __ _ _ _ #
+# / ____/ ____| ____| / _| | | | | | #
+# | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
+# \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
+# ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
+# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
+#-----------------------------------------------------------------------------#
+
+# commutative operations
+
+"fAdd" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
+},
+
+"fMul" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
+},
+
+"fMax" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
+},
+
+"fMin" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
+},
+
+"fAnd" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE And: And(a, b) = a AND b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
+},
+
+"fOr" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Or: Or(a, b) = a OR b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
+},
+
+"fEor" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
+},
+