+%flags = (
+ CF => { reg => "eflags", bit => 0 },
+ PF => { reg => "eflags", bit => 2 },
+ AF => { reg => "eflags", bit => 4 },
+ ZF => { reg => "eflags", bit => 6 },
+ SF => { reg => "eflags", bit => 7 },
+ TF => { reg => "eflags", bit => 8 },
+ IF => { reg => "eflags", bit => 9 },
+ DF => { reg => "eflags", bit => 10 },
+ OF => { reg => "eflags", bit => 11 },
+ IOPL0 => { reg => "eflags", bit => 12 },
+ IOPL1 => { reg => "eflags", bit => 13 },
+ NT => { reg => "eflags", bit => 14 },
+ RF => { reg => "eflags", bit => 16 },
+ VM => { reg => "eflags", bit => 17 },
+ AC => { reg => "eflags", bit => 18 },
+ VIF => { reg => "eflags", bit => 19 },
+ VIP => { reg => "eflags", bit => 20 },
+ ID => { reg => "eflags", bit => 21 },
+
+ FP_IE => { reg => "fpsw", bit => 0 },
+ FP_DE => { reg => "fpsw", bit => 1 },
+ FP_ZE => { reg => "fpsw", bit => 2 },
+ FP_OE => { reg => "fpsw", bit => 3 },
+ FP_UE => { reg => "fpsw", bit => 4 },
+ FP_PE => { reg => "fpsw", bit => 5 },
+ FP_SF => { reg => "fpsw", bit => 6 },
+ FP_ES => { reg => "fpsw", bit => 7 },
+ FP_C0 => { reg => "fpsw", bit => 8 },
+ FP_C1 => { reg => "fpsw", bit => 9 },
+ FP_C2 => { reg => "fpsw", bit => 10 },
+ FP_TOP0 => { reg => "fpsw", bit => 11 },
+ FP_TOP1 => { reg => "fpsw", bit => 12 },
+ FP_TOP2 => { reg => "fpsw", bit => 13 },
+ FP_C3 => { reg => "fpsw", bit => 14 },
+ FP_B => { reg => "fpsw", bit => 15 },
+
+ FP_IM => { reg => "fpcw", bit => 0 },
+ FP_DM => { reg => "fpcw", bit => 1 },
+ FP_ZM => { reg => "fpcw", bit => 2 },
+ FP_OM => { reg => "fpcw", bit => 3 },
+ FP_UM => { reg => "fpcw", bit => 4 },
+ FP_PM => { reg => "fpcw", bit => 5 },
+ FP_PC0 => { reg => "fpcw", bit => 8 },
+ FP_PC1 => { reg => "fpcw", bit => 9 },
+ FP_RC0 => { reg => "fpcw", bit => 10 },
+ FP_RC1 => { reg => "fpcw", bit => 11 },
+ FP_X => { reg => "fpcw", bit => 12 }
+); # %flags
+
+%cpu = (
+ GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
+ SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
+ VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
+ BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
+); # %cpu
+
+%vliw = (
+ bundle_size => 1,
+ bundels_per_cycle => 1
+); # vliw
+
+%emit_templates = (
+ S0 => "${arch}_emit_source_register(env, node, 0);",
+ S1 => "${arch}_emit_source_register(env, node, 1);",
+ S2 => "${arch}_emit_source_register(env, node, 2);",
+ S3 => "${arch}_emit_source_register(env, node, 3);",
+ S4 => "${arch}_emit_source_register(env, node, 4);",
+ S5 => "${arch}_emit_source_register(env, node, 5);",
+ D0 => "${arch}_emit_dest_register(env, node, 0);",
+ D1 => "${arch}_emit_dest_register(env, node, 1);",
+ D2 => "${arch}_emit_dest_register(env, node, 2);",
+ D3 => "${arch}_emit_dest_register(env, node, 3);",
+ D4 => "${arch}_emit_dest_register(env, node, 4);",
+ D5 => "${arch}_emit_dest_register(env, node, 5);",
+ X0 => "${arch}_emit_x87_name(env, node, 0);",
+ X1 => "${arch}_emit_x87_name(env, node, 1);",
+ X2 => "${arch}_emit_x87_name(env, node, 2);",
+ C => "${arch}_emit_immediate(env, node);",
+ SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
+ ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
+ ia32_emit_mode_suffix(env, node);",
+ M => "${arch}_emit_mode_suffix(env, node);",
+ XM => "${arch}_emit_x87_mode_suffix(env, node);",
+ XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
+ XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
+ AM => "${arch}_emit_am(env, node);",
+ unop0 => "${arch}_emit_unop(env, node, 0);",
+ unop1 => "${arch}_emit_unop(env, node, 1);",
+ unop2 => "${arch}_emit_unop(env, node, 2);",
+ unop3 => "${arch}_emit_unop(env, node, 3);",
+ unop4 => "${arch}_emit_unop(env, node, 4);",
+ DAM0 => "${arch}_emit_am_or_dest_register(env, node, 0);",
+ DAM1 => "${arch}_emit_am_or_dest_register(env, node, 0);",
+ binop => "${arch}_emit_binop(env, node);",
+ x87_binop => "${arch}_emit_x87_binop(env, node);",
+);
+