+Conv_FP2I => {
+ reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
+ latency => 10,
+ units => [ "SSE" ],
+ mode => $mode_gp,
+},
+
+Conv_FP2FP => {
+ reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
+ latency => 8,
+ units => [ "SSE" ],
+ mode => "mode_E",
+},
+
+CmpCMov => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
+ ins => [ "cmp_left", "cmp_right", "val_true", "val_false" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 2,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+xCmpCMov => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
+ latency => 5,
+ units => [ "SSE" ],
+ mode => $mode_gp,
+},
+
+vfCmpCMov => {
+ irn_flags => "R",
+ reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+ latency => 10,
+ units => [ "VFP" ],
+ mode => $mode_gp,
+ attr_type => "ia32_x87_attr_t",
+},
+
+CmpSet => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 2,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+xCmpSet => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
+ latency => 5,
+ units => [ "SSE" ],
+ mode => $mode_gp,
+},
+
+vfCmpSet => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
+ latency => 10,
+ units => [ "VFP" ],
+ mode => $mode_gp,
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfCMov => {
+ irn_flags => "R",
+ reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
+ latency => 10,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+#----------------------------------------------------------#
+# _ _ _ __ _ _ #
+# (_) | | | | / _| | | | #
+# __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
+# \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
+# \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
+# \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
+# | | #
+# _ __ ___ __| | ___ ___ #
+# | '_ \ / _ \ / _` |/ _ \/ __| #
+# | | | | (_) | (_| | __/\__ \ #
+# |_| |_|\___/ \__,_|\___||___/ #
+#----------------------------------------------------------#
+
+vfadd => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfmul => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+l_vfmul => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ arity => 2,
+},
+
+vfsub => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+l_vfsub => {
+ cmp_attr => "return 1;",
+ arity => 2,
+},
+
+vfdiv => {
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ outs => [ "res", "M" ],
+ latency => 20,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
+},
+
+l_vfdiv => {
+ cmp_attr => "return 1;",
+ outs => [ "res", "M" ],
+ arity => 2,
+},
+
+vfprem => {
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ latency => 20,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+l_vfprem => {
+ cmp_attr => "return 1;",
+ arity => 2,
+},
+
+vfabs => {
+ irn_flags => "R",
+ reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ ins => [ "value" ],
+ latency => 2,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfchs => {
+ irn_flags => "R",
+ reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ ins => [ "value" ],
+ latency => 2,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+# virtual Load and Store
+
+vfld => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "res", "M" ],
+ attr => "ir_mode *store_mode",
+ init_attr => "attr->attr.ls_mode = store_mode;",
+ latency => 2,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfst => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ attr => "ir_mode *store_mode",
+ init_attr => "attr->attr.ls_mode = store_mode;",
+ latency => 2,
+ units => [ "VFP" ],
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+},
+
+# Conversions
+
+vfild => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ outs => [ "res", "M" ],
+ ins => [ "base", "index", "mem" ],
+ latency => 4,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
+},
+
+l_vfild => {
+ cmp_attr => "return 1;",
+ outs => [ "res", "M" ],
+ arity => 2,
+},
+
+vfist => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
+ ins => [ "base", "index", "val", "fpcw", "mem" ],
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+},
+
+l_vfist => {
+ cmp_attr => "return 1;",
+ state => "exc_pinned",
+ arity => 3,
+ mode => "mode_M",
+},
+
+
+# constants
+
+vfldz => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfld1 => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfldpi => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfldln2 => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfldlg2 => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfldl2t => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfldl2e => {
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 4,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+vfConst => {
+ op_flags => "c",
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
+ latency => 3,
+ units => [ "VFP" ],
+ mode => "mode_E",
+ attr_type => "ia32_x87_attr_t",
+},
+
+# other
+
+vfCondJmp => {
+ state => "pinned",
+ op_flags => "L|X|Y",
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
+ outs => [ "false", "true", "temp_reg_eax" ],
+ latency => 10,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
+},
+
+#------------------------------------------------------------------------#
+# ___ _____ __ _ _ _ #
+# __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
+# \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
+# > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
+# /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
+#------------------------------------------------------------------------#
+
+# Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
+# are swapped, we work this around in the emitter...
+
+fadd => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fadd%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+faddp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. faddp %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fmul => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fmul%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fmulp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fmulp %x87_binop',,
+ attr_type => "ia32_x87_attr_t",
+},
+
+fsub => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fsub%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fsubp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+# see note about gas bugs
+ emit => '. fsubrp %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fsubr => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fsubr%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fsubrp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ irn_flags => "R",
+ reg_req => { },
+# see note about gas bugs
+ emit => '. fsubp %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fprem => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fprem1',
+ attr_type => "ia32_x87_attr_t",
+},
+
+# this node is just here, to keep the simulator running
+# we can omit this when a fprem simulation function exists
+fpremp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fprem1',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fdiv => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fdiv%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fdivp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+# see note about gas bugs
+ emit => '. fdivrp %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fdivr => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fdivr%XM %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fdivrp => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+# see note about gas bugs
+ emit => '. fdivp %x87_binop',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fabs => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fabs',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fchs => {
+ op_flags => "R|K",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fchs',
+ attr_type => "ia32_x87_attr_t",
+},
+
+# x87 Load and Store
+
+fld => {
+ rd_constructor => "NONE",
+ op_flags => "R|L|F",
+ state => "exc_pinned",
+ reg_req => { },
+ emit => '. fld%XM %AM',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fst => {
+ rd_constructor => "NONE",
+ op_flags => "R|L|F",
+ state => "exc_pinned",
+ reg_req => { },
+ emit => '. fst%XM %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+},
+
+fstp => {
+ rd_constructor => "NONE",
+ op_flags => "R|L|F",
+ state => "exc_pinned",
+ reg_req => { },
+ emit => '. fstp%XM %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+},
+
+# Conversions
+
+fild => {
+ op_flags => "R",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fild%XM %AM',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fist => {
+ op_flags => "R",
+ state => "exc_pinned",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fist%XM %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+},
+
+fistp => {
+ op_flags => "R",
+ state => "exc_pinned",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fistp%XM %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+},
+
+# constants
+
+fldz => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fldz',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fld1 => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fld1',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fldpi => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fldpi',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fldln2 => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fldln2',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fldlg2 => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fldlg2',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fldl2t => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fldll2t',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fldl2e => {
+ op_flags => "R|c|K",
+ irn_flags => "R",
+ reg_req => { },
+ emit => '. fldl2e',
+ attr_type => "ia32_x87_attr_t",
+},
+
+# fxch, fpush, fpop
+# Note that it is NEVER allowed to do CSE on these nodes
+# Moreover, note the virtual register requierements!
+
+fxch => {
+ op_flags => "R|K",
+ reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. fxch %X0',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fpush => {
+ op_flags => "R|K",
+ reg_req => {},
+ cmp_attr => "return 1;",
+ emit => '. fld %X0',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fpushCopy => {
+ op_flags => "R",
+ reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ cmp_attr => "return 1;",
+ emit => '. fld %X0',
+ attr_type => "ia32_x87_attr_t",
+},
+
+fpop => {
+ op_flags => "R|K",
+ reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. fstp %X0',
+ attr_type => "ia32_x87_attr_t",
+},
+
+# compare
+
+fcomJmp => {
+ op_flags => "L|X|Y",
+ reg_req => { },
+ attr_type => "ia32_x87_attr_t",
+},
+
+fcompJmp => {
+ op_flags => "L|X|Y",
+ reg_req => { },
+ attr_type => "ia32_x87_attr_t",
+},
+
+fcomppJmp => {
+ op_flags => "L|X|Y",
+ reg_req => { },
+ attr_type => "ia32_x87_attr_t",
+},
+
+fcomrJmp => {
+ op_flags => "L|X|Y",
+ reg_req => { },
+ attr_type => "ia32_x87_attr_t",
+},
+
+fcomrpJmp => {
+ op_flags => "L|X|Y",
+ reg_req => { },
+ attr_type => "ia32_x87_attr_t",
+},
+
+fcomrppJmp => {
+ op_flags => "L|X|Y",
+ reg_req => { },
+ attr_type => "ia32_x87_attr_t",
+},
+
+
+# -------------------------------------------------------------------------------- #
+# ____ ____ _____ _ _ #
+# / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
+# \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
+# ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
+# |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
+# #
+# -------------------------------------------------------------------------------- #
+
+
+# Spilling and reloading of SSE registers, hardcoded, not generated #
+
+xxLoad => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+ emit => '. movdqu %D0, %AM',
+ outs => [ "res", "M" ],
+ units => [ "SSE" ],
+},
+
+xxStore => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
+ emit => '. movdqu %binop',
+ units => [ "SSE" ],
+ mode => "mode_M",