-"Add" => {
- "irn_flags" => "R",
- "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
- "outs" => [ "res", "M" ],
-},
-
-"AddC" => {
- "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
- "outs" => [ "res", "M" ],
-},
-
-"l_Add" => {
- "op_flags" => "C",
- "irn_flags" => "R",
- "cmp_attr" => " return 1;\n",
- "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
- "arity" => 2,
-},
-
-"l_AddC" => {
- "op_flags" => "C",
- "cmp_attr" => " return 1;\n",
- "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
- "arity" => 2,
-},
-
-"MulS" => {
- "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
- "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
- "outs" => [ "EAX", "EDX", "M" ],
-},
-
-"l_MulS" => {
- "op_flags" => "C",
- "cmp_attr" => " return 1;\n",
- "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
- "outs" => [ "EAX", "EDX", "M" ],
- "arity" => 2
-},
-
-"Mul" => {
- "irn_flags" => "R",
- "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
- "outs" => [ "res", "M" ],
-},
-
-"l_Mul" => {
- "op_flags" => "C",
- "cmp_attr" => " return 1;\n",
- "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
- "arity" => 2
-},
-
-# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
-"Mulh" => {
- "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
- "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
- "outs" => [ "EAX", "EDX", "M" ],
-},
-
-"And" => {
- "irn_flags" => "R",
- "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
- "outs" => [ "res", "M" ],
-},
-
-"Or" => {
- "irn_flags" => "R",
- "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
- "outs" => [ "res", "M" ],
-},
-
-"Eor" => {
- "irn_flags" => "R",
- "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
- "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
- "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
- "outs" => [ "res", "M" ],
-},
-
-"l_Eor" => {
- "op_flags" => "C",
- "cmp_attr" => " return 1;\n",
- "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
- "arity" => 2
-},
-
-"Max" => {
- "irn_flags" => "R",
- "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
- "emit" =>
-'2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
- if (mode_is_signed(get_irn_mode(n))) {
-4. cmovl %D1, %S2 /* %S1 is less %S2 */
- }
- else {
-4. cmovb %D1, %S2 /* %S1 is below %S2 */
- }
-'
-},
-
-"Min" => {
- "irn_flags" => "R",
- "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
- "emit" =>
-'2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
- if (mode_is_signed(get_irn_mode(n))) {
-2. cmovg %D1, %S2 /* %S1 is greater %S2 */
- }
- else {
-2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
- }
-'
+Add => {
+ irn_flags => "R",
+ comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. addl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Adc => {
+ comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. adcl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Add64Bit => {
+ irn_flags => "R",
+ comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
+ arity => 4,
+ reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
+ emit => '
+. movl %S1, %D1
+. movl %S2, %D2
+. addl %S3, %D1
+. adcl %S4, %D2
+',
+ outs => [ "low_res", "high_res" ],
+ units => [ "GP" ],
+},
+
+l_Add => {
+ op_flags => "C",
+ irn_flags => "R",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
+ arity => 2,
+},
+
+l_Adc => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
+ arity => 2,
+},
+
+Mul => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
+ comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
+ reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ emit => '. mull %unop',
+ outs => [ "EAX", "EDX", "M" ],
+ latency => 10,
+ units => [ "GP" ],
+},
+
+l_Mul => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
+ outs => [ "EAX", "EDX", "M" ],
+ arity => 2
+},
+
+IMul => {
+ irn_flags => "R",
+ comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. imull %binop',
+ latency => 5,
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+IMul1OP => {
+ irn_flags => "R",
+ comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
+ reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ emit => '. imull %unop',
+ outs => [ "EAX", "EDX", "M" ],
+ latency => 5,
+ units => [ "GP" ],
+},
+
+l_IMul => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
+ arity => 2
+},
+
+And => {
+ irn_flags => "R",
+ comment => "construct And: And(a, b) = And(b, a) = a AND b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. andl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Or => {
+ irn_flags => "R",
+ comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. orl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+Xor => {
+ irn_flags => "R",
+ comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ emit => '. xorl %binop',
+ units => [ "GP" ],
+ mode => "mode_Iu",
+},
+
+l_Xor => {
+ op_flags => "C",
+ cmp_attr => "return 1;",
+ comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
+ arity => 2