+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "gp", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "operand" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
+ emit => '. bsr%M %unop3, %D0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
+#
+# SSE4.2 or SSE4a popcnt instruction
+#
+Popcnt => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "gp", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "operand" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
+ emit => '. popcnt%M %unop3, %D0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
+Call => {
+ state => "exc_pinned",
+ reg_req => {
+ in => [ "gp", "gp", "none", "gp", "esp", "fpcw", "eax", "ecx", "edx" ],
+ out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ]
+ },
+ ins => [ "base", "index", "mem", "addr", "stack", "fpcw", "eax", "ecx", "edx" ],
+ outs => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ],
+ attr_type => "ia32_call_attr_t",
+ attr => "unsigned pop, ir_type *call_tp",
+ am => "source,unary",
+ units => [ "BRANCH" ],
+ latency => 4, # random number
+ modified_flags => $status_flags
+},
+
+#
+# a Helper node for frame-climbing, needed for __builtin_(frame|return)_address
+#
+# PS: try gcc __builtin_frame_address(100000) :-)
+#
+ClimbFrame => {
+ reg_req => { in => [ "gp", "gp", "gp"], out => [ "in_r3" ] },
+ ins => [ "frame", "cnt", "tmp" ],
+ outs => [ "res" ],
+ latency => 4, # random number
+ attr_type => "ia32_climbframe_attr_t",
+ attr => "unsigned count",
+ units => [ "GP" ],
+ mode => $mode_gp
+},
+
+#
+# bswap
+#
+Bswap => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1" ] },
+ emit => '. bswap%M %S0',
+ ins => [ "val" ],
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+},
+
+#
+# bswap16, use xchg here
+#
+Bswap16 => {
+ irn_flags => "R",
+ reg_req => { in => [ "eax ebx ecx edx" ],
+ out => [ "in_r1" ] },
+ emit => '. xchg %SB0, %SH0',
+ ins => [ "val" ],
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+},
+
+#
+# BreakPoint
+#
+Breakpoint => {
+ state => "pinned",
+ reg_req => { in => [ "none" ], out => [ "none" ] },
+ ins => [ "mem" ],
+ latency => 0,
+ emit => ". int3",
+ units => [ "GP" ],
+ mode => mode_M,
+},
+
+#
+# Undefined Instruction on ALL x86 CPU's
+#
+UD2 => {
+ state => "pinned",
+ reg_req => { in => [ "none" ], out => [ "none" ] },
+ ins => [ "mem" ],
+ latency => 0,
+ emit => ". .value 0x0b0f",
+ units => [ "GP" ],
+ mode => mode_M,
+},
+
+#
+# outport
+#
+Outport => {
+ irn_flags => "R",
+ state => "pinned",
+ reg_req => { in => [ "edx", "eax", "none" ], out => [ "none" ] },
+ ins => [ "port", "value", "mem" ],
+ emit => '. out%M %SS0, %SI1',
+ units => [ "GP" ],
+ latency => 1,
+ mode => mode_M,
+ modified_flags => $status_flags
+},
+
+#
+# inport
+#
+Inport => {
+ irn_flags => "R",
+ state => "pinned",
+ reg_req => { in => [ "edx", "none" ], out => [ "eax", "none" ] },
+ ins => [ "port", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. in%M %DS0, %SS0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => mode_T,
+ modified_flags => $status_flags
+},
+
+#
+# Intel style prefetching
+#
+Prefetch0 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetcht0 %AM",
+ units => [ "GP" ],
+},
+
+Prefetch1 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetcht1 %AM",
+ units => [ "GP" ],
+},
+
+Prefetch2 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetcht2 %AM",
+ units => [ "GP" ],
+},
+
+PrefetchNTA => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetchnta %AM",
+ units => [ "GP" ],
+},
+
+#
+# 3DNow! prefetch instructions
+#
+Prefetch => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetch %AM",
+ units => [ "GP" ],
+},
+
+PrefetchW => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetchw %AM",
+ units => [ "GP" ],
+},
+
+#-----------------------------------------------------------------------------#
+# _____ _____ ______ __ _ _ _ #
+# / ____/ ____| ____| / _| | | | | | #
+# | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
+# \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
+# ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
+# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
+#-----------------------------------------------------------------------------#
+
+# produces a 0/+0.0
+xZero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. xorp%XSD %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+xPzero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pxor %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# produces all 1 bits
+xAllOnes => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pcmpeqb %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, dword
+xPslld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. pslld %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, qword
+xPsllq => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psllq %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift right, dword
+xPsrld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psrld %SI1, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# mov from integer to SSE register
+xMovd => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp" ], out => [ "xmm" ] },
+ emit => '. movd %S0, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# commutative operations
+
+xAdd => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
+ emit => '. add%XXM %binop',
+ latency => 4,
+ units => [ "SSE" ],
+ mode => $mode_xmm