+ int offset = get_ia32_am_offs_int(node);
+ ir_entity *entity = get_ia32_am_sc(node);
+
+ return offset == 1 && entity == NULL;
+}
+
+static int is_am_minus_one(const ir_node *node)
+{
+ int offset = get_ia32_am_offs_int(node);
+ ir_entity *entity = get_ia32_am_sc(node);
+
+ return offset == -1 && entity == NULL;
+}
+
+/**
+ * Transforms a LEA into an Add or SHL if possible.
+ */
+static void peephole_ia32_Lea(ir_node *node)
+{
+ const arch_env_t *arch_env = cg->arch_env;
+ ir_graph *irg = current_ir_graph;
+ ir_node *base;
+ ir_node *index;
+ const arch_register_t *base_reg;
+ const arch_register_t *index_reg;
+ const arch_register_t *out_reg;
+ int scale;
+ int has_immediates;
+ ir_node *op1;
+ ir_node *op2;
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_node *res;
+ ir_node *noreg;
+ ir_node *nomem;
+
+ assert(is_ia32_Lea(node));
+
+ /* we can only do this if are allowed to globber the flags */
+ if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
+ return;
+
+ base = get_irn_n(node, n_ia32_Lea_base);
+ index = get_irn_n(node, n_ia32_Lea_index);
+
+ if(is_noreg(cg, base)) {
+ base = NULL;
+ base_reg = NULL;
+ } else {
+ base_reg = arch_get_irn_register(arch_env, base);
+ }
+ if(is_noreg(cg, index)) {
+ index = NULL;
+ index_reg = NULL;
+ } else {
+ index_reg = arch_get_irn_register(arch_env, index);
+ }
+
+ if(base == NULL && index == NULL) {
+ /* we shouldn't construct these in the first place... */
+#ifdef DEBUG_libfirm
+ ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
+#endif
+ return;
+ }
+
+ out_reg = arch_get_irn_register(arch_env, node);
+ scale = get_ia32_am_scale(node);
+ assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
+ /* check if we have immediates values (frame entities should already be
+ * expressed in the offsets) */
+ if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
+ has_immediates = 1;
+ } else {
+ has_immediates = 0;
+ }
+
+ /* we can transform leas where the out register is the same as either the
+ * base or index register back to an Add or Shl */
+ if(out_reg == base_reg) {
+ if(index == NULL) {
+#ifdef DEBUG_libfirm
+ if(!has_immediates) {
+ ir_fprintf(stderr, "Optimisation warning: found lea which is "
+ "just a copy\n");
+ }
+#endif
+ op1 = base;
+ goto make_add_immediate;
+ }
+ if(scale == 0 && !has_immediates) {
+ op1 = base;
+ op2 = index;
+ goto make_add;
+ }
+ /* can't create an add */
+ return;
+ } else if(out_reg == index_reg) {
+ if(base == NULL) {
+ if(has_immediates && scale == 0) {
+ op1 = index;
+ goto make_add_immediate;
+ } else if(!has_immediates && scale > 0) {
+ op1 = index;
+ op2 = create_immediate_from_int(cg, scale);
+ goto make_shl;
+ } else if(!has_immediates) {
+#ifdef DEBUG_libfirm
+ ir_fprintf(stderr, "Optimisation warning: found lea which is "
+ "just a copy\n");
+#endif
+ }
+ } else if(scale == 0 && !has_immediates) {
+ op1 = index;
+ op2 = base;
+ goto make_add;
+ }
+ /* can't create an add */
+ return;
+ } else {
+ /* can't create an add */
+ return;
+ }
+
+make_add_immediate:
+ if(ia32_cg_config.use_incdec) {
+ if(is_am_one(node)) {
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ res = new_rd_ia32_Inc(dbgi, irg, block, op1);
+ arch_set_irn_register(arch_env, res, out_reg);
+ goto exchange;
+ }
+ if(is_am_minus_one(node)) {
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ res = new_rd_ia32_Dec(dbgi, irg, block, op1);
+ arch_set_irn_register(arch_env, res, out_reg);
+ goto exchange;
+ }
+ }
+ op2 = create_immediate_from_am(cg, node);
+
+make_add:
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ noreg = ia32_new_NoReg_gp(cg);
+ nomem = new_NoMem();
+ res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
+ arch_set_irn_register(arch_env, res, out_reg);
+ set_ia32_commutative(res);
+ goto exchange;
+
+make_shl:
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ noreg = ia32_new_NoReg_gp(cg);
+ nomem = new_NoMem();
+ res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
+ arch_set_irn_register(arch_env, res, out_reg);
+ goto exchange;
+
+exchange:
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
+
+ /* add new ADD/SHL to schedule */
+ DBG_OPT_LEA2ADD(node, res);
+
+ /* exchange the Add and the LEA */
+ be_peephole_before_exchange(node, res);
+ sched_add_before(node, res);
+ sched_remove(node);
+ exchange(node, res);
+ be_peephole_after_exchange(res);
+}
+
+/**
+ * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
+ */
+static void peephole_ia32_Imul_split(ir_node *imul) {
+ const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
+ const arch_register_t *reg;
+ ir_node *load, *block, *base, *index, *mem, *res, *noreg;
+ dbg_info *dbgi;
+ ir_graph *irg;
+
+ if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
+ /* no memory, imm form ignore */
+ return;
+ }
+ /* we need a free register */
+ reg = get_free_gp_reg();
+ if (reg == NULL)
+ return;
+
+ /* fine, we can rebuild it */
+ dbgi = get_irn_dbg_info(imul);
+ block = get_nodes_block(imul);
+ irg = current_ir_graph;
+ base = get_irn_n(imul, n_ia32_IMul_base);
+ index = get_irn_n(imul, n_ia32_IMul_index);
+ mem = get_irn_n(imul, n_ia32_IMul_mem);
+ load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+
+ /* copy all attributes */
+ set_irn_pinned(load, get_irn_pinned(imul));
+ set_ia32_op_type(load, ia32_AddrModeS);
+ set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
+
+ set_ia32_am_scale(load, get_ia32_am_scale(imul));
+ set_ia32_am_sc(load, get_ia32_am_sc(imul));
+ set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
+ if (is_ia32_am_sc_sign(imul))
+ set_ia32_am_sc_sign(load);
+ if (is_ia32_use_frame(imul))
+ set_ia32_use_frame(load);
+ set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
+
+ sched_add_before(imul, load);
+
+ mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
+ res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+
+ arch_set_irn_register(arch_env, res, reg);
+ be_peephole_after_exchange(res);
+
+ set_irn_n(imul, n_ia32_IMul_mem, mem);
+ noreg = get_irn_n(imul, n_ia32_IMul_left);
+ set_irn_n(imul, n_ia32_IMul_left, res);
+ set_ia32_op_type(imul, ia32_Normal);
+}
+
+/**
+ * Replace xorps r,r and xorpd r,r by pxor r,r
+ */
+static void peephole_ia32_xZero(ir_node *xor) {
+ set_irn_op(xor, op_ia32_xPzero);
+}
+
+/**
+ * Register a peephole optimisation function.
+ */
+static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {