projects
/
libfirm
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
no need for no_float_fold hack anymore
[libfirm]
/
ir
/
be
/
ia32
/
ia32_optimize.c
diff --git
a/ir/be/ia32/ia32_optimize.c
b/ir/be/ia32/ia32_optimize.c
index
801f8aa
..
f3eba30
100644
(file)
--- a/
ir/be/ia32/ia32_optimize.c
+++ b/
ir/be/ia32/ia32_optimize.c
@@
-34,9
+34,10
@@
#include "tv.h"
#include "irgmod.h"
#include "irgwalk.h"
#include "tv.h"
#include "irgmod.h"
#include "irgwalk.h"
-#include "height.h"
+#include "height
s
.h"
#include "irbitset.h"
#include "irprintf.h"
#include "irbitset.h"
#include "irprintf.h"
+#include "irdump.h"
#include "error.h"
#include "../be_t.h"
#include "error.h"
#include "../be_t.h"
@@
-57,8
+58,6
@@
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-static ia32_code_gen_t *cg;
-
static void copy_mark(const ir_node *old, ir_node *new)
{
if (is_ia32_is_reload(old))
static void copy_mark(const ir_node *old, ir_node *new)
{
if (is_ia32_is_reload(old))
@@
-145,6
+144,7
@@
check_shift_amount:
static void peephole_ia32_Cmp(ir_node *const node)
{
ir_node *right;
static void peephole_ia32_Cmp(ir_node *const node)
{
ir_node *right;
+ ir_graph *irg;
ia32_immediate_attr_t const *imm;
dbg_info *dbgi;
ir_node *block;
ia32_immediate_attr_t const *imm;
dbg_info *dbgi;
ir_node *block;
@@
-171,8
+171,9
@@
static void peephole_ia32_Cmp(ir_node *const node)
return;
dbgi = get_irn_dbg_info(node);
return;
dbgi = get_irn_dbg_info(node);
+ irg = get_irn_irg(node);
block = get_nodes_block(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(
c
g);
+ noreg = ia32_new_NoReg_gp(
ir
g);
nomem = get_irg_no_mem(current_ir_graph);
op = get_irn_n(node, n_ia32_Cmp_left);
attr = get_irn_generic_attr(node);
nomem = get_irg_no_mem(current_ir_graph);
op = get_irn_n(node, n_ia32_Cmp_left);
attr = get_irn_generic_attr(node);
@@
-265,8
+266,8
@@
static void peephole_ia32_Test(ir_node *node)
int pnc = get_ia32_condcode(user);
switch (pnc) {
int pnc = get_ia32_condcode(user);
switch (pnc) {
- case pn_Cmp_Eq: pnc = ia32_pn_Cmp_no_carry; break;
- case pn_Cmp_Lg: pnc = ia32_pn_Cmp_carry; break;
+ case pn_Cmp_Eq: pnc = ia32_pn_Cmp_no
t
_carry; break;
+ case pn_Cmp_Lg: pnc = ia32_pn_Cmp_carry;
break;
default: panic("unexpected pn");
}
set_ia32_condcode(user, pnc);
default: panic("unexpected pn");
}
set_ia32_condcode(user, pnc);
@@
-477,13
+478,13
@@
static void peephole_IncSP_Store_to_push(ir_node *irn)
/* walk through the Stores and create Pushs for them */
block = get_nodes_block(irn);
spmode = get_irn_mode(irn);
/* walk through the Stores and create Pushs for them */
block = get_nodes_block(irn);
spmode = get_irn_mode(irn);
- irg =
cg->irg
;
+ irg =
get_irn_irg(irn)
;
for (; i >= 0; --i) {
const arch_register_t *spreg;
ir_node *push;
ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i];
for (; i >= 0; --i) {
const arch_register_t *spreg;
ir_node *push;
ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i];
- ir_node *noreg = ia32_new_NoReg_gp(
c
g);
+ ir_node *noreg = ia32_new_NoReg_gp(
ir
g);
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
val = get_irn_n(store, n_ia32_unary_op);
mem = get_irn_n(store, n_ia32_mem);
@@
-770,7
+771,7
@@
static void peephole_Load_IncSP_to_pop(ir_node *irn)
/* create a new IncSP if needed */
block = get_nodes_block(irn);
/* create a new IncSP if needed */
block = get_nodes_block(irn);
- irg =
cg->irg
;
+ irg =
get_irn_irg(irn)
;
if (inc_ofs > 0) {
pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
sched_add_before(irn, pred_sp);
if (inc_ofs > 0) {
pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
sched_add_before(irn, pred_sp);
@@
-970,9
+971,9
@@
static void peephole_ia32_Const(ir_node *node)
be_peephole_exchange(node, xor);
}
be_peephole_exchange(node, xor);
}
-static inline int is_noreg(
ia32_code_gen_t *cg,
const ir_node *node)
+static inline int is_noreg(const ir_node *node)
{
{
- return
node == cg->noreg_gp
;
+ return
is_ia32_NoReg_GP(node)
;
}
ir_node *ia32_immediate_from_long(long val)
}
ir_node *ia32_immediate_from_long(long val)
@@
-1023,6
+1024,7
@@
static int is_am_minus_one(const ir_node *node)
*/
static void peephole_ia32_Lea(ir_node *node)
{
*/
static void peephole_ia32_Lea(ir_node *node)
{
+ ir_graph *irg;
ir_node *base;
ir_node *index;
const arch_register_t *base_reg;
ir_node *base;
ir_node *index;
const arch_register_t *base_reg;
@@
-1047,13
+1049,13
@@
static void peephole_ia32_Lea(ir_node *node)
base = get_irn_n(node, n_ia32_Lea_base);
index = get_irn_n(node, n_ia32_Lea_index);
base = get_irn_n(node, n_ia32_Lea_base);
index = get_irn_n(node, n_ia32_Lea_index);
- if (is_noreg(
cg,
base)) {
+ if (is_noreg(base)) {
base = NULL;
base_reg = NULL;
} else {
base_reg = arch_get_irn_register(base);
}
base = NULL;
base_reg = NULL;
} else {
base_reg = arch_get_irn_register(base);
}
- if (is_noreg(
cg,
index)) {
+ if (is_noreg(index)) {
index = NULL;
index_reg = NULL;
} else {
index = NULL;
index_reg = NULL;
} else {
@@
-1148,7
+1150,8
@@
make_add_immediate:
make_add:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
make_add:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
+ irg = get_irn_irg(node);
+ noreg = ia32_new_NoReg_gp(irg);
nomem = new_NoMem();
res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
arch_set_irn_register(res, out_reg);
nomem = new_NoMem();
res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
arch_set_irn_register(res, out_reg);
@@
-1158,7
+1161,8
@@
make_add:
make_shl:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
make_shl:
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
- noreg = ia32_new_NoReg_gp(cg);
+ irg = get_irn_irg(node);
+ noreg = ia32_new_NoReg_gp(irg);
nomem = new_NoMem();
res = new_bd_ia32_Shl(dbgi, block, op1, op2);
arch_set_irn_register(res, out_reg);
nomem = new_NoMem();
res = new_bd_ia32_Shl(dbgi, block, op1, op2);
arch_set_irn_register(res, out_reg);
@@
-1243,10
+1247,8
@@
static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
}
/* Perform peephole-optimizations. */
}
/* Perform peephole-optimizations. */
-void ia32_peephole_optimization(i
a32_code_gen_t *new_c
g)
+void ia32_peephole_optimization(i
r_graph *ir
g)
{
{
- cg = new_cg;
-
/* register peephole optimisations */
clear_irp_opcodes_generic_func();
register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
/* register peephole optimisations */
clear_irp_opcodes_generic_func();
register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
@@
-1264,7
+1266,7
@@
void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
if (ia32_cg_config.use_short_sex_eax)
register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
if (ia32_cg_config.use_short_sex_eax)
register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
- be_peephole_opt(
cg->b
irg);
+ be_peephole_opt(irg);
}
/**
}
/**
@@
-1415,7
+1417,8
@@
static void optimize_conv_conv(ir_node *node)
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
set_irn_op(pred, op_ia32_Conv_I2I8Bit);
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
set_irn_op(pred, op_ia32_Conv_I2I8Bit);
- set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
+ arch_set_in_register_reqs(pred,
+ arch_get_in_register_reqs(node));
}
} else {
/* we don't want to end up with 2 loads, so we better do nothing */
}
} else {
/* we don't want to end up with 2 loads, so we better do nothing */
@@
-1429,7
+1432,8
@@
static void optimize_conv_conv(ir_node *node)
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
/* Argh:We must change the opcode to 8bit AND copy the register constraints */
if (get_mode_size_bits(conv_mode) == 8) {
set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
- set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
+ arch_set_in_register_reqs(result_conv,
+ arch_get_in_register_reqs(node));
}
}
} else {
}
}
} else {
@@
-1472,12
+1476,9
@@
static void optimize_node(ir_node *node, void *env)
/**
* Performs conv and address mode optimization.
*/
/**
* Performs conv and address mode optimization.
*/
-void ia32_optimize_graph(i
a32_code_gen_t *c
g)
+void ia32_optimize_graph(i
r_graph *ir
g)
{
{
- irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
-
- if (cg->dump)
- be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
+ irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
}
void ia32_init_optimize(void)
}
void ia32_init_optimize(void)