+ /* should have NO index */
+ if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
+ break;
+
+ offset = get_ia32_am_offs_int(node);
+ /* we should NEVER access uninitialized stack BELOW the current SP */
+ assert(offset >= 0);
+
+ /* storing at half-slots is bad */
+ if ((offset & 3) != 0)
+ break;
+
+ if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
+ continue;
+ /* ignore those outside the possible windows */
+ if (offset > inc_ofs - 4)
+ continue;
+ loadslot = offset >> 2;
+
+ /* loading from the same slot twice is bad (and shouldn't happen...) */
+ if (loads[loadslot] != NULL)
+ break;
+
+ dreg = arch_irn_get_register(node, pn_ia32_Load_res);
+ if (regmask & (1 << dreg->index)) {
+ /* this register is already used */
+ break;
+ }
+ regmask |= 1 << dreg->index;
+
+ loads[loadslot] = node;
+ if (loadslot > maxslot)
+ maxslot = loadslot;
+ }
+
+ if (maxslot < 0)
+ return;
+
+ /* find the first slot */
+ for (i = maxslot; i >= 0; --i) {
+ ir_node *load = loads[i];
+
+ if (load == NULL)
+ break;
+ }
+
+ ofs = inc_ofs - (maxslot + 1) * 4;
+ inc_ofs = (i+1) * 4;
+
+ /* create a new IncSP if needed */
+ block = get_nodes_block(irn);
+ irg = get_irn_irg(irn);
+ if (inc_ofs > 0) {
+ pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
+ sched_add_before(irn, pred_sp);
+ }
+
+ /* walk through the Loads and create Pops for them */
+ for (++i; i <= maxslot; ++i) {
+ ir_node *load = loads[i];
+ ir_node *mem, *pop;
+ const ir_edge_t *edge, *tmp;
+ const arch_register_t *reg;
+
+ mem = get_irn_n(load, n_ia32_mem);
+ reg = arch_irn_get_register(load, pn_ia32_Load_res);
+
+ pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
+ arch_irn_set_register(pop, pn_ia32_Load_res, reg);
+
+ copy_mark(load, pop);
+
+ /* create stackpointer Proj */
+ pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
+ arch_set_irn_register(pred_sp, esp);
+
+ sched_add_before(irn, pop);
+
+ /* rewire now */
+ foreach_out_edge_safe(load, edge, tmp) {
+ ir_node *proj = get_edge_src_irn(edge);
+
+ set_Proj_pred(proj, pop);
+ }
+
+ /* we can remove the Load now */
+ sched_remove(load);
+ kill_node(load);
+ }
+
+ be_set_IncSP_offset(irn, -ofs);
+ be_set_IncSP_pred(irn, pred_sp);
+}
+
+
+/**
+ * Find a free GP register if possible, else return NULL.
+ */
+static const arch_register_t *get_free_gp_reg(void)
+{
+ int i;
+
+ for (i = 0; i < N_ia32_gp_REGS; ++i) {
+ const arch_register_t *reg = &ia32_gp_regs[i];
+ if (arch_register_type_is(reg, ignore))
+ continue;
+
+ if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
+ return &ia32_gp_regs[i];
+ }
+
+ return NULL;
+}
+
+/**
+ * Creates a Pop instruction before the given schedule point.
+ *
+ * @param dbgi debug info
+ * @param block the block
+ * @param stack the previous stack value
+ * @param schedpoint the new node is added before this node
+ * @param reg the register to pop
+ *
+ * @return the new stack value
+ */
+static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
+ ir_node *stack, ir_node *schedpoint,
+ const arch_register_t *reg)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ ir_node *pop;
+ ir_node *keep;
+ ir_node *val;
+ ir_node *in[1];
+
+ pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack);
+
+ stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
+ arch_set_irn_register(stack, esp);
+ val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
+ arch_set_irn_register(val, reg);
+
+ sched_add_before(schedpoint, pop);
+
+ in[0] = val;
+ keep = be_new_Keep(block, 1, in);
+ sched_add_before(schedpoint, keep);
+
+ return stack;
+}
+
+/**
+ * Optimize an IncSp by replacing it with Push/Pop.
+ */
+static void peephole_be_IncSP(ir_node *node)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *reg;
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_node *stack;
+ int offset;
+
+ /* first optimize incsp->incsp combinations */
+ node = be_peephole_IncSP_IncSP(node);
+
+ /* transform IncSP->Store combinations to Push where possible */
+ peephole_IncSP_Store_to_push(node);
+
+ /* transform Load->IncSP combinations to Pop where possible */
+ peephole_Load_IncSP_to_pop(node);
+
+ if (arch_get_irn_register(node) != esp)
+ return;
+
+ /* replace IncSP -4 by Pop freereg when possible */
+ offset = be_get_IncSP_offset(node);
+ if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
+ (offset != -4 || ia32_cg_config.use_add_esp_4) &&
+ (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
+ (offset != +8 || ia32_cg_config.use_sub_esp_8))
+ return;
+
+ if (offset < 0) {
+ /* we need a free register for pop */
+ reg = get_free_gp_reg();
+ if (reg == NULL)
+ return;
+
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ stack = be_get_IncSP_pred(node);
+
+ stack = create_pop(dbgi, block, stack, node, reg);
+
+ if (offset == -8) {
+ stack = create_pop(dbgi, block, stack, node, reg);
+ }