+
+ /* we can remove the Load now */
+ sched_remove(load);
+ kill_node(load);
+ }
+
+ be_set_IncSP_offset(irn, -ofs);
+ be_set_IncSP_pred(irn, pred_sp);
+}
+
+
+/**
+ * Find a free GP register if possible, else return NULL.
+ */
+static const arch_register_t *get_free_gp_reg(void)
+{
+ int i;
+
+ for(i = 0; i < N_ia32_gp_REGS; ++i) {
+ const arch_register_t *reg = &ia32_gp_regs[i];
+ if(arch_register_type_is(reg, ignore))
+ continue;
+
+ if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
+ return &ia32_gp_regs[i];
+ }
+
+ return NULL;
+}
+
+/**
+ * Creates a Pop instruction before the given schedule point.
+ *
+ * @param dbgi debug info
+ * @param irg the graph
+ * @param block the block
+ * @param stack the previous stack value
+ * @param schedpoint the new node is added before this node
+ * @param reg the register to pop
+ *
+ * @return the new stack value
+ */
+static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
+ ir_node *stack, ir_node *schedpoint,
+ const arch_register_t *reg)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ ir_node *pop;
+ ir_node *keep;
+ ir_node *val;
+ ir_node *in[1];
+
+ pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
+
+ stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
+ arch_set_irn_register(stack, esp);
+ val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
+ arch_set_irn_register(val, reg);
+
+ sched_add_before(schedpoint, pop);
+
+ in[0] = val;
+ keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+ sched_add_before(schedpoint, keep);
+
+ return stack;
+}
+
+/**
+ * Creates a Push instruction before the given schedule point.
+ *
+ * @param dbgi debug info
+ * @param irg the graph
+ * @param block the block
+ * @param stack the previous stack value
+ * @param schedpoint the new node is added before this node
+ * @param reg the register to pop
+ *
+ * @return the new stack value
+ */
+static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
+ ir_node *stack, ir_node *schedpoint)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+
+ ir_node *val = ia32_new_Unknown_gp(cg);
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = get_irg_no_mem(irg);
+ ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
+ sched_add_before(schedpoint, push);
+
+ stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
+ arch_set_irn_register(stack, esp);
+
+ return stack;
+}
+
+/**
+ * Optimize an IncSp by replacing it with Push/Pop.
+ */
+static void peephole_be_IncSP(ir_node *node)
+{
+ const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *reg;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_node *stack;
+ int offset;
+
+ /* first optimize incsp->incsp combinations */
+ node = be_peephole_IncSP_IncSP(node);
+
+ /* transform IncSP->Store combinations to Push where possible */
+ peephole_IncSP_Store_to_push(node);
+
+ /* transform Load->IncSP combinations to Pop where possible */
+ peephole_Load_IncSP_to_pop(node);
+
+ if (arch_get_irn_register(node) != esp)
+ return;
+
+ /* replace IncSP -4 by Pop freereg when possible */
+ offset = be_get_IncSP_offset(node);
+ if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
+ (offset != -4 || ia32_cg_config.use_add_esp_4) &&
+ (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
+ (offset != +8 || ia32_cg_config.use_sub_esp_8))
+ return;
+
+ if (offset < 0) {
+ /* we need a free register for pop */
+ reg = get_free_gp_reg();
+ if (reg == NULL)