+ }
+
+ /* all ok, change to push */
+ dbgi = get_irn_dbg_info(store);
+ block = get_nodes_block(store);
+ noreg = ia32_new_NoReg_gp(cg);
+ val = get_irn_n(store, n_ia32_Store_val);
+
+ push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
+
+ create_push(dbgi, current_ir_graph, block, am_base, store);
+}
+#endif
+
+/**
+ * Return true if a mode can be stored in the GP register set
+ */
+static inline int mode_needs_gp_reg(ir_mode *mode)
+{
+ if (mode == ia32_mode_fpcw)
+ return 0;
+ if (get_mode_size_bits(mode) > 32)
+ return 0;
+ return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
+}
+
+/**
+ * Tries to create Pops from Load, IncSP combinations.
+ * The Loads are replaced by Pops, the IncSP is modified
+ * (possibly into IncSP 0, but not removed).
+ */
+static void peephole_Load_IncSP_to_pop(ir_node *irn)
+{
+ const arch_register_t *esp = &ia32_registers[REG_ESP];
+ int i, maxslot, inc_ofs, ofs;
+ ir_node *node, *pred_sp, *block;
+ ir_node *loads[MAXPUSH_OPTIMIZE];
+ unsigned regmask = 0;
+ unsigned copymask = ~0;
+
+ memset(loads, 0, sizeof(loads));
+ assert(be_is_IncSP(irn));
+
+ inc_ofs = -be_get_IncSP_offset(irn);
+ if (inc_ofs < 4)
+ return;
+
+ /*
+ * We first walk the schedule before the IncSP node as long as we find
+ * suitable Loads that could be transformed to a Pop.
+ * We save them into the stores array which is sorted by the frame offset/4
+ * attached to the node
+ */
+ maxslot = -1;
+ pred_sp = be_get_IncSP_pred(irn);
+ for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
+ int offset;
+ int loadslot;
+ const arch_register_t *sreg, *dreg;
+
+ /* it has to be a Load */
+ if (!is_ia32_Load(node)) {
+ if (be_is_Copy(node)) {
+ if (!mode_needs_gp_reg(get_irn_mode(node))) {
+ /* not a GP copy, ignore */
+ continue;
+ }
+ dreg = arch_get_irn_register(node);
+ sreg = arch_get_irn_register(be_get_Copy_op(node));
+ if (regmask & copymask & (1 << sreg->index)) {
+ break;
+ }
+ if (regmask & copymask & (1 << dreg->index)) {
+ break;
+ }
+ /* we CAN skip Copies if neither the destination nor the source
+ * is not in our regmask, ie none of our future Pop will overwrite it */
+ regmask |= (1 << dreg->index) | (1 << sreg->index);
+ copymask &= ~((1 << dreg->index) | (1 << sreg->index));
+ continue;
+ }
+ break;
+ }
+
+ /* we can handle only GP loads */
+ if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
+ continue;
+
+ /* it has to use our predecessor sp value */
+ if (get_irn_n(node, n_ia32_base) != pred_sp) {
+ /* it would be ok if this load does not use a Pop result,
+ * but we do not check this */
+ break;
+ }
+
+ /* should have NO index */
+ if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
+ break;
+
+ offset = get_ia32_am_offs_int(node);
+ /* we should NEVER access uninitialized stack BELOW the current SP */
+ assert(offset >= 0);
+
+ /* storing at half-slots is bad */
+ if ((offset & 3) != 0)
+ break;
+
+ if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
+ continue;
+ /* ignore those outside the possible windows */
+ if (offset > inc_ofs - 4)
+ continue;
+ loadslot = offset >> 2;
+
+ /* loading from the same slot twice is bad (and shouldn't happen...) */
+ if (loads[loadslot] != NULL)
+ break;
+
+ dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
+ if (regmask & (1 << dreg->index)) {
+ /* this register is already used */
+ break;