+ int am_offs; /**< offsets for AddrMode */
+ ir_entity *am_sc; /**< SymConst for AddrMode */
+
+ union {
+ tarval *tv; /**< tarval for immediate operations */
+ ir_entity *sc; /**< the symconst ident */
+ } cnst_val;
+
+ ir_mode *ls_mode; /**< Load/Store mode: This is the mode of the
+ value that is manipulated by this node. */
+
+ ir_entity *frame_ent; /**< the frame entity attached to this node */
+
+ long pn_code; /**< projnum "types" (e.g. indicate compare operators and argument numbers for switches) */
+
+ unsigned latency; /**< the latency of the instruction in clock cycles */
+
+#ifndef NDEBUG
+ const char *orig_node; /**< holds the name of the original ir node */
+ unsigned attr_type; /**< bitfield indicating the attribute type */
+#endif
+
+ const be_execution_unit_t ***exec_units; /**< list of units this operation can be executed on */
+
+ const arch_register_req_t **in_req; /**< register requirements for arguments */
+ const arch_register_req_t **out_req; /**< register requirements for results */
+
+ const arch_register_t **slots; /**< register slots for assigned registers */
+};
+COMPILETIME_ASSERT(sizeof(struct ia32_attr_data_bitfield) <= 4, attr_bitfield);
+
+typedef struct ia32_immediate_attr_t ia32_immediate_attr_t;
+struct ia32_immediate_attr_t {
+ ia32_attr_t attr;
+ ir_entity *symconst;
+ long offset;
+};
+
+typedef struct ia32_x87_attr_t ia32_x87_attr_t;
+struct ia32_x87_attr_t {
+ ia32_attr_t attr;
+ const arch_register_t *x87[3]; /**< register slots for x87 register */
+};
+
+typedef struct ia32_asm_attr_t ia32_asm_attr_t;
+struct ia32_asm_attr_t {
+ ia32_x87_attr_t x87_attr;
+ ident *asm_text;
+};
+
+/* the following union is necessary to indicate to the compiler that we might want to cast
+ * the structs (we use them to simulate OO-inheritance) */
+union allow_casts_attr_t_ {
+ ia32_attr_t attr;
+ ia32_x87_attr_t x87_attr;
+ ia32_asm_attr_t asm_attr;
+ ia32_immediate_attr_t immediate_attr;
+};