- const char *name, *p;
- ir_mode *mode = NULL;
- int bad = 0;
-
- switch (reason) {
- case dump_node_opcode_txt:
- name = get_irn_opname(n);
- fprintf(F, "%s", name);
- break;
-
- case dump_node_mode_txt:
- mode = get_irn_mode(n);
-
- if (mode == mode_BB || mode == mode_ANY || mode == mode_BAD || mode == mode_T) {
- mode = NULL;
- }
- else if (is_ia32_Load(n)) {
- mode = get_irn_mode(get_irn_n(n, 1));
- }
- else if (is_ia32_Store(n)) {
- mode = get_irn_mode(get_irn_n(n, 2));
- }
-
- if (mode)
- fprintf(F, "[%s]", get_mode_name(mode));
- break;
-
- case dump_node_nodeattr_txt:
- name = get_irn_opname(n);
- p = name + strlen(name) - 2;
- if (p[0] == '_' && p[1] == 'i') {
- tarval *tv = get_ia32_Immop_tarval(n);
- if (tv)
- fprintf_tv(F, tv, 1);
- else {
- fprintf(F, "[SymC &%s]", get_sc_name(get_ia32_old_ir(n)));
- }
- }
- else if (is_ia32_Call(n)) {
- ir_node *old_call = get_ia32_old_ir(n);
- ir_node *sc = get_Call_ptr(old_call);
-
- fprintf(F, "&%s ", get_sc_name(sc));
- }
- break;
-
- case dump_node_info_txt:
- if (is_ia32_Lea(n)) {
- tarval *o = get_ia32_offs(n);
- tarval *tv = get_ia32_Immop_tarval(n);
-
- fprintf(F, "LEA ");
- if (o)
- fprintf_tv(F, o, 0);
- fprintf(F, "(%s, %s", get_irn_opname(get_irn_n(n, 0)), get_irn_opname(get_irn_n(n, 1)));
- if (tv) {
- fprintf(F, ", ");
- fprintf_tv(F, tv, 0);
- }
- fprintf(F, ")\n");
- }
- break;
- }
-
- return bad;
+ ir_mode *mode = NULL;
+ int bad = 0;
+ int i, n_res, am_flav, flags;
+ const ia32_register_req_t **reqs;
+ const arch_register_t **slots;
+
+ switch (reason) {
+ case dump_node_opcode_txt:
+ fprintf(F, "%s", get_irn_opname(n));
+ break;
+
+ case dump_node_mode_txt:
+ mode = get_irn_mode(n);
+
+ if (is_ia32_Ld(n) || is_ia32_St(n)) {
+ mode = get_ia32_ls_mode(n);
+ }
+
+ fprintf(F, "[%s]", mode ? get_mode_name(mode) : "?NOMODE?");
+ break;
+
+ case dump_node_nodeattr_txt:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ char *pref = is_ia32_ImmSymConst(n) ? "SymC" : "";
+
+ fprintf(F, "[%s%s]", pref, get_ia32_cnst(n));
+ }
+
+ if (! is_ia32_Lea(n)) {
+ if (is_ia32_AddrModeS(n)) {
+ fprintf(F, "[AM S] ");
+ }
+ else if (is_ia32_AddrModeD(n)) {
+ fprintf(F, "[AM D] ");
+ }
+ }
+
+ break;
+
+ case dump_node_info_txt:
+ n_res = get_ia32_n_res(n);
+ fprintf(F, "=== IA32 attr begin ===\n");
+
+ /* dump IN requirements */
+ if (get_irn_arity(n) > 0) {
+ reqs = get_ia32_in_req_all(n);
+ dump_reg_req(F, n, reqs, 0);
+ }
+
+ /* dump OUT requirements */
+ if (n_res > 0) {
+ reqs = get_ia32_out_req_all(n);
+ dump_reg_req(F, n, reqs, 1);
+ }
+
+ /* dump assigned registers */
+ slots = get_ia32_slots(n);
+ if (slots && n_res > 0) {
+ for (i = 0; i < n_res; i++) {
+ fprintf(F, "reg #%d = %s\n", i, slots[i] ? slots[i]->name : "n/a");
+ }
+ fprintf(F, "\n");
+ }
+
+ /* dump op type */
+ fprintf(F, "op = ");
+ switch (get_ia32_op_type(n)) {
+ case ia32_Normal:
+ fprintf(F, "Normal");
+ break;
+ case ia32_Const:
+ fprintf(F, "Const");
+ break;
+ case ia32_SymConst:
+ fprintf(F, "SymConst");
+ break;
+ case ia32_AddrModeD:
+ fprintf(F, "AM Dest (Load+Store)");
+ break;
+ case ia32_AddrModeS:
+ fprintf(F, "AM Source (Load)");
+ break;
+ default:
+ fprintf(F, "unknown (%d)", get_ia32_op_type(n));
+ break;
+ }
+ fprintf(F, "\n");
+
+
+ /* dump supported am */
+ fprintf(F, "AM support = ");
+ switch (get_ia32_am_support(n)) {
+ case ia32_am_None:
+ fprintf(F, "none");
+ break;
+ case ia32_am_Source:
+ fprintf(F, "source only (Load)");
+ break;
+ case ia32_am_Dest:
+ fprintf(F, "dest only (Load+Store)");
+ break;
+ case ia32_am_Full:
+ fprintf(F, "full");
+ break;
+ default:
+ fprintf(F, "unknown (%d)", get_ia32_am_support(n));
+ break;
+ }
+ fprintf(F, "\n");
+
+ /* dump am flavour */
+ fprintf(F, "AM flavour =");
+ am_flav = get_ia32_am_flavour(n);
+ if (am_flav == ia32_am_N) {
+ fprintf(F, " none");
+ }
+ else {
+ if (am_flav & ia32_O) {
+ fprintf(F, " O");
+ }
+ if (am_flav & ia32_B) {
+ fprintf(F, " B");
+ }
+ if (am_flav & ia32_I) {
+ fprintf(F, " I");
+ }
+ if (am_flav & ia32_S) {
+ fprintf(F, " S");
+ }
+ }
+ fprintf(F, " (%d)\n", am_flav);
+
+ /* dump AM offset */
+ fprintf(F, "AM offset = ");
+ if (get_ia32_am_offs(n)) {
+ fprintf(F, "%s", get_ia32_am_offs(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+ /* dump AM scale */
+ fprintf(F, "AM scale = %d\n", get_ia32_am_scale(n));
+
+ /* dump pn code */
+ fprintf(F, "pn_code = %ld\n", get_ia32_pncode(n));
+
+ /* dump n_res */
+ fprintf(F, "n_res = %d\n", get_ia32_n_res(n));
+
+ /* dump use_frame */
+ fprintf(F, "use_frame = %d\n", is_ia32_use_frame(n));
+
+ /* commutative */
+ fprintf(F, "commutative = %d\n", is_ia32_commutative(n));
+
+ /* dump flags */
+ fprintf(F, "flags =");
+ flags = get_ia32_flags(n);
+ if (flags == arch_irn_flags_none) {
+ fprintf(F, " none");
+ }
+ else {
+ if (flags & arch_irn_flags_dont_spill) {
+ fprintf(F, " unspillable");
+ }
+ if (flags & arch_irn_flags_rematerializable) {
+ fprintf(F, " remat");
+ }
+ if (flags & arch_irn_flags_ignore) {
+ fprintf(F, " ignore");
+ }
+ }
+ fprintf(F, " (%d)\n", flags);
+
+ /* dump frame entity */
+ fprintf(F, "frame entity = ");
+ if (get_ia32_frame_ent(n)) {
+ ir_fprintf(F, "%+F", get_ia32_frame_ent(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+
+#ifndef NDEBUG
+ /* dump original ir node name */
+ fprintf(F, "orig node = ");
+ if (get_ia32_orig_node(n)) {
+ fprintf(F, "%s", get_ia32_orig_node(n));
+ }
+ else {
+ fprintf(F, "n/a");
+ }
+ fprintf(F, "\n");
+#endif /* NDEBUG */
+
+ fprintf(F, "=== IA32 attr end ===\n");
+ /* end of: case dump_node_info_txt */
+ break;
+ }
+
+ return bad;