+/**
+ * Checks if node is a Store or fStore.
+ */
+int is_ia32_St(const ir_node *node) {
+ return is_ia32_Store(node) || is_ia32_fStore(node);
+}
+
+/**
+ * Returns the name of the OUT register at position pos.
+ */
+const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+
+ assert(is_ia32_irn(node) && "Not an ia32 node.");
+ assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(attr->slots[pos] && "No register assigned");
+
+ return arch_register_get_name(attr->slots[pos]);
+}
+
+/**
+ * Returns the index of the OUT register at position pos within its register class.
+ */
+int get_ia32_out_regnr(const ir_node *node, int pos) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+
+ assert(is_ia32_irn(node) && "Not an ia32 node.");
+ assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(attr->slots[pos] && "No register assigned");
+
+ return arch_register_get_index(attr->slots[pos]);
+}
+
+/**
+ * Returns the OUT register at position pos.
+ */
+const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+
+ assert(is_ia32_irn(node) && "Not an ia32 node.");
+ assert(pos < attr->data.n_res && "Invalid OUT position.");
+ assert(attr->slots[pos] && "No register assigned");
+
+ return attr->slots[pos];
+}
+
+/**
+ * Allocates num register slots for node.
+ */
+void alloc_ia32_reg_slots(ir_node *node, int num) {
+ ia32_attr_t *attr = get_ia32_attr(node);
+
+ if (num) {
+ attr->slots = xcalloc(num, sizeof(attr->slots[0]));
+ }
+ else {
+ attr->slots = NULL;
+ }
+
+ attr->data.n_res;
+}
+
+/**
+ * Initializes the nodes attributes.
+ */
+void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs,
+ const ia32_register_req_t **out_reqs, int n_res)
+{
+ set_ia32_flags(node, flags);
+ set_ia32_in_req_all(node, in_reqs);
+ set_ia32_out_req_all(node, out_reqs);
+ alloc_ia32_reg_slots(node, n_res);
+}