- const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
- int same_pos = reqs[i]->other_same;
-
- /*
- there is a constraint for the remaining operand
- and the result register is equal to base or index register
- */
- if (same_pos == 2 &&
- (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
- {
- /* turn back address mode */
- ir_node *in_node = get_irn_n(irn, 2);
- const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
- ir_node *block = get_nodes_block(irn);
- ir_mode *ls_mode = get_ia32_ls_mode(irn);
- ir_node *load;
- int pnres;
-
- if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
- load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
- pnres = pn_ia32_Load_res;
- }
- else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
- load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
- pnres = pn_ia32_xLoad_res;
- }
- else {
- panic("cannot turn back address mode for this register class");
+ const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
+ int same_pos = get_first_same(reqs[i]);
+ ir_node *same_node = get_irn_n(irn, same_pos);
+ const arch_register_t *same_reg
+ = arch_get_irn_register(arch_env, same_node);
+ ir_graph *irg = cg->irg;
+ dbg_info *dbgi = get_irn_dbg_info(irn);
+ ir_node *block = get_nodes_block(irn);
+ ir_node *load;
+ ir_node *load_res;
+ ir_node *mem;
+
+ /* should_be same constraint is fullfilled, nothing to do */
+ if (out_reg == same_reg)
+ continue;
+
+ /* we only need to do something if the out reg is the same as base
+ or index register */
+ if (out_reg != reg_base && out_reg != reg_index)
+ continue;
+
+ /* turn back address mode */
+ mem = get_irn_n(irn, n_ia32_mem);
+ assert(get_irn_mode(mem) == mode_M);
+ load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+
+ /* copy address mode information to load */
+ set_ia32_op_type(load, ia32_AddrModeS);
+ ia32_copy_am_attrs(load, irn);
+ if (is_ia32_is_reload(irn))
+ set_ia32_is_reload(load);
+
+ /* insert the load into schedule */
+ sched_add_before(irn, load);
+
+ DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
+
+ load_res = new_r_Proj(cg->irg, block, load, mode_Iu, pn_ia32_Load_res);
+ arch_set_irn_register(cg->arch_env, load_res, out_reg);
+
+ /* set the new input operand */
+ if (is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right)))
+ set_irn_n(irn, n_ia32_binary_left, load_res);
+ else
+ set_irn_n(irn, n_ia32_binary_right, load_res);
+ if (get_irn_mode(irn) == mode_T) {
+ const ir_edge_t *edge, *next;
+ foreach_out_edge_safe(irn, edge, next) {
+ ir_node *node = get_edge_src_irn(edge);
+ int pn = get_Proj_proj(node);
+ if (pn == pn_ia32_res) {
+ exchange(node, irn);
+ } else if (pn == pn_ia32_mem) {
+ set_Proj_pred(node, load);
+ set_Proj_proj(node, pn_ia32_Load_M);
+ } else {
+ panic("Unexpected Proj");
+ }