#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_dbg_stat.h"
{
ir_graph *irg;
ir_node *in1, *in2, *noreg, *nomem, *res;
{
ir_graph *irg;
ir_node *in1, *in2, *noreg, *nomem, *res;
- noreg = ia32_new_NoReg_gp(cg);
- noreg_fp = ia32_new_NoReg_xmm(cg);
- nomem = new_rd_NoMem(cg->irg);
+ irg = get_irn_irg(irn);
+ noreg = ia32_new_NoReg_gp(irg);
+ noreg_fp = ia32_new_NoReg_xmm(irg);
+ nomem = new_r_NoMem(irg);
in1 = get_irn_n(irn, n_ia32_binary_left);
in2 = get_irn_n(irn, n_ia32_binary_right);
in1 = get_irn_n(irn, n_ia32_binary_left);
in2 = get_irn_n(irn, n_ia32_binary_right);
- in1_reg = arch_get_irn_register(cg->arch_env, in1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2);
- out_reg = get_ia32_out_reg(irn, 0);
+ in1_reg = arch_get_irn_register(in1);
+ in2_reg = arch_get_irn_register(in2);
+ out_reg = arch_irn_get_register(irn, 0);
- res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp);
+ res = new_bd_ia32_xXor(dbg, block, noreg, noreg, nomem, in2, noreg_fp);
size = get_mode_size_bits(op_mode);
entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
set_ia32_am_sc(res, entity);
set_ia32_op_type(res, ia32_AddrModeS);
set_ia32_ls_mode(res, op_mode);
size = get_mode_size_bits(op_mode);
entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
set_ia32_am_sc(res, entity);
set_ia32_op_type(res, ia32_AddrModeS);
set_ia32_ls_mode(res, op_mode);
- res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1);
+ res = new_bd_ia32_xAdd(dbg, block, noreg, noreg, nomem, res, in1);
set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
/* exchange the add and the sub */
set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
/* exchange the add and the sub */
- res = new_rd_ia32_Neg(dbg, irg, block, in2);
- arch_set_irn_register(cg->arch_env, res, in2_reg);
+ res = new_bd_ia32_Neg(dbg, block, in2);
+ arch_set_irn_register(res, in2_reg);
- res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
- arch_set_irn_register(cg->arch_env, res, out_reg);
+ res = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, res, in1);
+ arch_set_irn_register(res, out_reg);
- ir_node *stc, *cmc, *not, *adc;
+ ir_node *stc, *cmc, *nnot, *adc;
- not = new_rd_ia32_Not(dbg, irg, block, in2);
- arch_set_irn_register(cg->arch_env, not, in2_reg);
- sched_add_before(irn, not);
+ nnot = new_bd_ia32_Not(dbg, block, in2);
+ arch_set_irn_register(nnot, in2_reg);
+ sched_add_before(irn, nnot);
- stc = new_rd_ia32_Stc(dbg, irg, block);
- arch_set_irn_register(cg->arch_env, stc,
- &ia32_flags_regs[REG_EFLAGS]);
+ stc = new_bd_ia32_Stc(dbg, block);
+ arch_set_irn_register(stc, &ia32_registers[REG_EFLAGS]);
- adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not,
- in1, stc);
- arch_set_irn_register(cg->arch_env, adc, out_reg);
+ adc = new_bd_ia32_Adc(dbg, block, noreg, noreg, nomem, nnot, in1, stc);
+ arch_set_irn_register(adc, out_reg);
sched_add_before(irn, adc);
set_irn_mode(adc, mode_T);
sched_add_before(irn, adc);
set_irn_mode(adc, mode_T);
- adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags);
- arch_set_irn_register(cg->arch_env, adc_flags,
- &ia32_flags_regs[REG_EFLAGS]);
+ adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
+ arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
- cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags);
- arch_set_irn_register(cg->arch_env, cmc,
- &ia32_flags_regs[REG_EFLAGS]);
+ cmc = new_bd_ia32_Cmc(dbg, block, adc_flags);
+ arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
sched_add_before(irn, cmc);
exchange(flags_proj, cmc);
sched_add_before(irn, cmc);
exchange(flags_proj, cmc);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
+ set_irn_mode(res, get_irn_mode(irn));
+
+ SET_IA32_ORIG_NODE(res, irn);
const arch_register_t *out_reg, *in_reg;
int n_res, i;
ir_node *in_node, *block;
const arch_register_t *out_reg, *in_reg;
int n_res, i;
ir_node *in_node, *block;
block = get_nodes_block(node);
/* check all OUT requirements, if there is a should_be_same */
block = get_nodes_block(node);
/* check all OUT requirements, if there is a should_be_same */
- out_reg = get_ia32_out_reg(node, i);
- in_node = get_irn_n(node, same_pos);
- in_reg = arch_get_irn_register(arch_env, in_node);
+ out_reg = arch_irn_get_register(node, i);
+ in_node = get_irn_n(node, same_pos);
+ in_reg = arch_get_irn_register(in_node);
- ir_node *copy = be_new_Copy(cls, irg, block, in_node);
+ ir_node *copy = be_new_Copy(cls, block, in_node);
/* insert copy before the node into the schedule */
sched_add_before(node, copy);
/* insert copy before the node into the schedule */
sched_add_before(node, copy);
- perm = be_new_Perm(cls, irg, block, 2, in);
+ perm = be_new_Perm(cls, block, 2, in);
- perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
- perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
+ perm_proj0 = new_r_Proj(perm, get_irn_mode(in[0]), 0);
+ perm_proj1 = new_r_Proj(perm, get_irn_mode(in[1]), 1);
- arch_set_irn_register(arch_env, perm_proj0, out_reg);
- arch_set_irn_register(arch_env, perm_proj1, in_reg);
+ arch_set_irn_register(perm_proj0, out_reg);
+ arch_set_irn_register(perm_proj1, in_reg);
* register -> base or index is broken then.
* Solution: Turn back this address mode into explicit Load + Operation.
*/
* register -> base or index is broken then.
* Solution: Turn back this address mode into explicit Load + Operation.
*/
- const arch_register_t *out_reg;
- int same_pos;
- ir_node *same_node;
- const arch_register_t *same_reg;
- ir_node *load_res;
+ const arch_register_req_t *req = arch_get_out_register_req(irn, i);
+ const arch_register_t *out_reg;
+ int same_pos;
+ ir_node *same_node;
+ const arch_register_t *same_reg;
+ ir_node *load_res;
- out_reg = get_ia32_out_reg(irn, i);
- same_pos = get_first_same(reqs[i]);
+ out_reg = arch_irn_get_register(irn, i);
+ same_pos = get_first_same(req);
- if (out_reg != arch_get_irn_register(arch_env, get_irn_n(irn, n_ia32_base)) &&
- out_reg != arch_get_irn_register(arch_env, get_irn_n(irn, n_ia32_index)))
+ if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
+ out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
- load_res = turn_back_am(irn);
- arch_set_irn_register(cg->arch_env, load_res, out_reg);
+ load_res = ia32_turn_back_am(irn);
+ arch_set_irn_register(load_res, out_reg);
/* first: turn back AM source if necessary */
for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
next = sched_next(irn);
/* first: turn back AM source if necessary */
for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
next = sched_next(irn);
next = sched_next(irn);
/* check if there is a sub which need to be transformed */
if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
next = sched_next(irn);
/* check if there is a sub which need to be transformed */
if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
/* some nodes are just a bit less efficient, but need no fixing if the
* should be same requirement is not fulfilled */
if (need_constraint_copy(irn))
/* some nodes are just a bit less efficient, but need no fixing if the
* should be same requirement is not fulfilled */
if (need_constraint_copy(irn))
irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
while (! waitq_empty(wq)) {
irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
while (! waitq_empty(wq)) {
- ir_node *block = waitq_get(wq);
- ia32_finish_irg_walker(block, cg);
+ ir_node *block = (ir_node*)waitq_get(wq);
+ ia32_finish_irg_walker(block, NULL);