- ir_node *copy, *in_node, *block, *in2_node;
- ia32_op_type_t op_tp;
-
- if (is_ia32_irn(irn)) {
- /* AM Dest nodes don't produce any values */
- op_tp = get_ia32_op_type(irn);
- if (op_tp == ia32_AddrModeD)
- goto end;
-
- reqs = get_ia32_out_req_all(irn);
- n_res = get_ia32_n_res(irn);
- block = get_nodes_block(irn);
-
- /* check all OUT requirements, if there is a should_be_same */
- if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
- {
- for (i = 0; i < n_res; i++) {
- if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
- /* get in and out register */
- out_reg = get_ia32_out_reg(irn, i);
- in_node = get_irn_n(irn, reqs[i]->same_pos);
- in_reg = arch_get_irn_register(cg->arch_env, in_node);
-
- /* don't copy ignore nodes */
- if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
- continue;
-
- /* check if in and out register are equal */
- if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
- /* in case of a commutative op: just exchange the in's */
- /* beware: the current op could be everything, so test for ia32 */
- /* commutativity first before getting the second in */
- if (is_ia32_commutative(irn)) {
- in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
-
- if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
- set_irn_n(irn, reqs[i]->same_pos, in2_node);
- set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
- }
- else
- goto insert_copy;
- }
- else {
-insert_copy:
- DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
- /* create copy from in register */
- copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
-
- DBG_OPT_2ADDRCPY(copy);
-
- /* destination is the out register */
- arch_set_irn_register(cg->arch_env, copy, out_reg);
-
- /* insert copy before the node into the schedule */
- sched_add_before(irn, copy);
-
- /* set copy as in */
- set_irn_n(irn, reqs[i]->same_pos, copy);
- }
- }
- }
+ ir_node *in_node, *block;
+
+ reqs = get_ia32_out_req_all(node);
+ n_res = get_ia32_n_res(node);
+ block = get_nodes_block(node);
+
+ /* check all OUT requirements, if there is a should_be_same */
+ for (i = 0; i < n_res; i++) {
+ int i2, arity;
+ int same_pos;
+ ir_node *perm;
+ ir_node *in[2];
+ ir_node *perm_proj0;
+ ir_node *perm_proj1;
+ ir_node *uses_out_reg;
+ const arch_register_req_t *req = reqs[i];
+ const arch_register_class_t *cls;
+ int uses_out_reg_pos;
+
+ if (!arch_register_req_is(req, should_be_same))
+ continue;
+
+ same_pos = get_first_same(req);
+
+ /* get in and out register */
+ out_reg = get_ia32_out_reg(node, i);
+ in_node = get_irn_n(node, same_pos);
+ in_reg = arch_get_irn_register(arch_env, in_node);
+
+ /* requirement already fulfilled? */
+ if (in_reg == out_reg)
+ continue;
+ /* unknowns can be changed to any register we want on emitting */
+ if (is_unknown_reg(in_reg))
+ continue;
+ cls = arch_register_get_class(in_reg);
+ assert(cls == arch_register_get_class(out_reg));
+
+ /* check if any other input operands uses the out register */
+ arity = get_irn_arity(node);
+ uses_out_reg = NULL;
+ uses_out_reg_pos = -1;
+ for(i2 = 0; i2 < arity; ++i2) {
+ ir_node *in = get_irn_n(node, i2);
+ const arch_register_t *in_reg;
+
+ if(!mode_is_data(get_irn_mode(in)))
+ continue;
+
+ in_reg = arch_get_irn_register(arch_env, in);
+
+ if(in_reg != out_reg)
+ continue;
+
+ if(uses_out_reg != NULL && in != uses_out_reg) {
+ panic("invalid register allocation");