- ir_node *copy, *in_node, *block, *in2_node;
- ia32_op_type_t op_tp;
-
- if (is_ia32_irn(irn)) {
- /* AM Dest nodes don't produce any values */
- op_tp = get_ia32_op_type(irn);
- if (op_tp == ia32_AddrModeD)
- goto end;
-
- reqs = get_ia32_out_req_all(irn);
- n_res = get_ia32_n_res(irn);
- block = get_nodes_block(irn);
-
- /* check all OUT requirements, if there is a should_be_same */
- if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
- {
- for (i = 0; i < n_res; i++) {
- if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
- /* get in and out register */
- out_reg = get_ia32_out_reg(irn, i);
- in_node = get_irn_n(irn, reqs[i]->same_pos);
- in_reg = arch_get_irn_register(cg->arch_env, in_node);
-
- /* don't copy ignore nodes */
- if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
- continue;
-
- /* check if in and out register are equal */
- if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
- /* in case of a commutative op: just exchange the in's */
- /* beware: the current op could be everything, so test for ia32 */
- /* commutativity first before getting the second in */
- if (is_ia32_commutative(irn)) {
- in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
-
- if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
- set_irn_n(irn, reqs[i]->same_pos, in2_node);
- set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
- }
- else
- goto insert_copy;
- }
- else {
-insert_copy:
- DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
- /* create copy from in register */
- copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
-
- DBG_OPT_2ADDRCPY(copy);
-
- /* destination is the out register */
- arch_set_irn_register(cg->arch_env, copy, out_reg);
-
- /* insert copy before the node into the schedule */
- sched_add_before(irn, copy);
-
- /* set copy as in */
- set_irn_n(irn, reqs[i]->same_pos, copy);
- }
+
+ /* check only ia32 nodes with source address mode */
+ if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
+ return;
+ /* only need to fix binary operations */
+ if (get_ia32_am_arity(irn) != ia32_am_binary)
+ return;
+
+ base = get_irn_n(irn, 0);
+ index = get_irn_n(irn, 1);
+
+ reg_base = arch_get_irn_register(arch_env, base);
+ reg_index = arch_get_irn_register(arch_env, index);
+ reqs = get_ia32_out_req_all(irn);
+
+ noreg = ia32_new_NoReg_gp(cg);
+
+ n_res = get_ia32_n_res(irn);
+
+ for (i = 0; i < n_res; i++) {
+ if (arch_register_req_is(reqs[i], should_be_same)) {
+ /* get in and out register */
+ const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
+ int same_pos = get_first_same(reqs[i]);
+ ir_node *same_node = get_irn_n(irn, same_pos);
+ const arch_register_t *same_reg
+ = arch_get_irn_register(arch_env, same_node);
+ const arch_register_class_t *same_cls;
+ ir_graph *irg = cg->irg;
+ dbg_info *dbgi = get_irn_dbg_info(irn);
+ ir_node *block = get_nodes_block(irn);
+ ir_mode *proj_mode;
+ ir_node *load;
+ ir_node *load_res;
+ ir_node *mem;
+ int pnres;
+ int pnmem;
+
+ /* should_be same constraint is fullfilled, nothing to do */
+ if(out_reg == same_reg)
+ continue;
+
+ /* we only need to do something if the out reg is the same as base
+ or index register */
+ if (out_reg != reg_base && out_reg != reg_index)
+ continue;
+
+ /* turn back address mode */
+ same_cls = arch_register_get_class(same_reg);
+ mem = get_irn_n(irn, n_ia32_mem);
+ assert(get_irn_mode(mem) == mode_M);
+ if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) {
+ load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+ pnres = pn_ia32_Load_res;
+ pnmem = pn_ia32_Load_M;
+ proj_mode = mode_Iu;
+ } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem,
+ get_ia32_ls_mode(irn));
+ pnres = pn_ia32_xLoad_res;
+ pnmem = pn_ia32_xLoad_M;
+ proj_mode = mode_E;
+ } else {
+ panic("cannot turn back address mode for this register class");
+ }
+
+ /* copy address mode information to load */
+ set_ia32_op_type(load, ia32_AddrModeS);
+ ia32_copy_am_attrs(load, irn);
+
+ /* insert the load into schedule */
+ sched_add_before(irn, load);
+
+ DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
+
+ load_res = new_r_Proj(cg->irg, block, load, proj_mode, pnres);
+ arch_set_irn_register(cg->arch_env, load_res, out_reg);
+
+ /* set the new input operand */
+ set_irn_n(irn, n_ia32_binary_right, load_res);
+ if(get_irn_mode(irn) == mode_T) {
+ const ir_edge_t *edge, *next;
+ foreach_out_edge_safe(irn, edge, next) {
+ ir_node *node = get_edge_src_irn(edge);
+ int pn = get_Proj_proj(node);
+ if(pn == 0) {
+ exchange(node, irn);
+ } else if(pn == pn_ia32_mem) {
+ set_Proj_pred(node, load);
+ set_Proj_proj(node, pnmem);