+ else {
+ const arch_register_t *in1 = get_in_reg(n, 2);
+ const arch_register_t *in2 = get_in_reg(n, 3);
+ const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
+ const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
+
+ if (is_ia32_emit_cl(n)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
+ in_name = "cl";
+ }
+
+ snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
+ }
+ break;
+ case ia32_AddrModeS:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
+ }
+ else {
+ if (PRODUCES_RESULT(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
+ }
+ else {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
+ }
+ }
+ break;
+ case ia32_AddrModeD:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
+ ia32_emit_am(n, env),
+ is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
+ get_ia32_cnst(n)); /* tell the assembler to store it's address. */
+ }
+ else {
+ const arch_register_t *in1 = get_in_reg(n, 2);
+ ir_mode *mode = get_ia32_res_mode(n);
+ const char *in_name;
+
+ mode = mode ? mode : get_ia32_ls_mode(n);
+ in_name = ia32_get_reg_name_for_mode(env, mode, in1);
+
+ if (is_ia32_emit_cl(n)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
+ in_name = "cl";
+ }
+
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
+ }
+ break;
+ default:
+ assert(0 && "unsupported op type");
+ }
+
+#undef PRODUCES_RESULT
+
+ return buf;
+}
+
+/**
+ * Emits registers and/or address mode of a binary operation.
+ */
+char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+ static char *buf = NULL;
+
+ /* verify that this function is never called on non-AM supporting operations */
+ //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
+
+ if (! buf) {
+ buf = xcalloc(1, SNPRINTF_BUF_LEN);
+ }
+ else {
+ memset(buf, 0, SNPRINTF_BUF_LEN);
+ }
+
+ switch(get_ia32_op_type(n)) {
+ case ia32_Normal:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+ }
+ else {
+ ia32_attr_t *attr = get_ia32_attr(n);
+ const arch_register_t *in1 = attr->x87[0];
+ const arch_register_t *in2 = attr->x87[1];
+ const arch_register_t *out = attr->x87[2];
+ const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
+
+ snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
+ }
+ break;
+ case ia32_AddrModeS:
+ case ia32_AddrModeD:
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+ break;
+ default:
+ assert(0 && "unsupported op type");
+ }
+
+#undef PRODUCES_RESULT
+
+ return buf;
+}
+
+/**
+ * Emits registers and/or address mode of a unary operation.
+ */
+char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
+ static char *buf = NULL;
+
+ if (! buf) {
+ buf = xcalloc(1, SNPRINTF_BUF_LEN);
+ }
+ else {
+ memset(buf, 0, SNPRINTF_BUF_LEN);
+ }
+
+ switch(get_ia32_op_type(n)) {
+ case ia32_Normal:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
+ }
+ else {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
+ }
+ break;
+ case ia32_AddrModeD:
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+ break;
+ default:
+ assert(0 && "unsupported op type");
+ }
+
+ return buf;
+}
+
+/**
+ * Emits address mode.
+ */
+char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
+ ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
+ int had_output = 0;
+ char *s;
+ int size;
+ static struct obstack *obst = NULL;
+ ir_mode *mode = get_ia32_ls_mode(n);
+
+ if (! is_ia32_Lea(n))
+ assert(mode && "AM node must have ls_mode attribute set.");
+
+ if (! obst) {
+ obst = xcalloc(1, sizeof(*obst));
+ }
+ else {
+ obstack_free(obst, NULL);
+ }
+
+ /* obstack_free with NULL results in an uninitialized obstack */
+ obstack_init(obst);
+
+ if (mode) {
+ switch (get_mode_size_bits(mode)) {
+ case 8:
+ obstack_printf(obst, "BYTE PTR ");
+ break;
+ case 16:
+ obstack_printf(obst, "WORD PTR ");
+ break;
+ case 32:
+ obstack_printf(obst, "DWORD PTR ");
+ break;
+ case 64:
+ if (has_x87_register(n))
+ /* ARGHHH: stupid gas x87 wants QWORD PTR but SSE must be WITHOUT */
+ obstack_printf(obst, "QWORD PTR ");
+ break;
+ case 80:
+ case 96:
+ obstack_printf(obst, "XWORD PTR ");
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* emit address mode symconst */
+ if (get_ia32_am_sc(n)) {
+ if (is_ia32_am_sc_sign(n))
+ obstack_printf(obst, "-");
+ obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
+ }
+
+ if (am_flav & ia32_B) {
+ obstack_printf(obst, "[");
+ lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
+ had_output = 1;
+ }
+
+ if (am_flav & ia32_I) {
+ if (had_output) {
+ obstack_printf(obst, "+");