+ assert(cls1 == cls2 && "Register class mismatch at Perm");
+
+ if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
+#if 0
+ if(emit_env->isa->opt_arch == arch_athlon) {
+ // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
+ // it is often beneficial to use the 3 xor trick instead of an xchg
+ cmnt_buf[0] = 0;
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
+ IA32_DO_EMIT(irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
+ IA32_DO_EMIT(irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
+ } else {
+#endif
+ be_emit_cstring(env, "\txchg ");
+ ia32_emit_source_register(env, node, 1);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ be_emit_finish_line_gas(env, node);
+#if 0
+ }
+#endif
+ } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ be_emit_cstring(env, "\txorpd ");
+ ia32_emit_source_register(env, node, 1);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ be_emit_finish_line_gas(env, NULL);
+
+ be_emit_cstring(env, "\txorpd ");
+ ia32_emit_source_register(env, node, 0);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 1);
+ be_emit_finish_line_gas(env, NULL);
+
+ be_emit_cstring(env, "\txorpd ");
+ ia32_emit_source_register(env, node, 1);
+ be_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ be_emit_finish_line_gas(env, node);
+ } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ /* is a NOP */
+ } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
+ /* is a NOP */
+ }