+/**
+ * Emits code for conditional SSE floating point jump with two variables.
+ */
+static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
+ lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+ IA32_DO_EMIT(irn);
+ finish_CondJmp(F, irn, mode_F);
+
+}
+
+/**
+ * Emits code for conditional x87 floating point jump with two variables.
+ */
+static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ ia32_attr_t *attr = get_ia32_attr(irn);
+ const char *reg = attr->x87[1]->name;
+ const char *instr = "fcom";
+ int reverse = 0;
+
+ switch (get_ia32_pncode(irn)) {
+ case iro_ia32_fcomrJmp:
+ reverse = 1;
+ case iro_ia32_fcomJmp:
+ default:
+ instr = "fucom";
+ break;
+ case iro_ia32_fcomrpJmp:
+ reverse = 1;
+ case iro_ia32_fcompJmp:
+ instr = "fucomp";
+ break;
+ case iro_ia32_fcomrppJmp:
+ reverse = 1;
+ case iro_ia32_fcomppJmp:
+ instr = "fucompp";
+ reg = "";
+ break;
+ }
+
+ if (reverse)
+ set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg);
+ lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+ IA32_DO_EMIT(irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
+ IA32_DO_EMIT(irn);
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
+ IA32_DO_EMIT(irn);
+
+ finish_CondJmp(F, irn, mode_Is);
+}
+
+static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
+ int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
+ int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *in1, *in2, *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov));
+ in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov));
+
+ /* we have to emit the cmp first, because the destination register */
+ /* could be one of the compare registers */
+ if (is_ia32_CmpCMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+ }
+ else if (is_ia32_xCmpCMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+ }
+ else if (is_PsiCondCMov) {
+ /* omit compare because flags are already set by And/Or */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
+ }
+ else {
+ assert(0 && "unsupported CMov");
+ }
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ if (REGS_ARE_EQUAL(out, in2)) {
+ /* best case: default in == out -> do nothing */
+ }
+ else if (REGS_ARE_EQUAL(out, in1)) {
+ /* true in == out -> need complement compare and exchange true and default in */
+ ir_node *t = get_irn_n(irn, 2);
+ set_irn_n(irn, 2, get_irn_n(irn, 3));
+ set_irn_n(irn, 3, t);
+
+ cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), is_unsigned);
+
+ }
+ else {
+ /* out is different from in: need copy default -> out */
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
+ IA32_DO_EMIT(irn);
+ }
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
+ const char *reg8bit;
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
+
+ if (is_ia32_CmpSet(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
+ }
+ else if (is_ia32_xCmpSet(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
+ }
+ else if (is_ia32_PsiCondSet(irn)) {
+ /* omit compare because flags are already set by And/Or */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
+ }
+ else {
+ assert(0 && "unsupported Set");
+ }
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ /* use mov to clear target because it doesn't affect the eflags */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
+ IA32_DO_EMIT(irn);
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
+}
+
+static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
+}
+
+static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
+}
+
+static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ int sse_pnc = -1;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+
+ switch (get_ia32_pncode(irn)) {
+ case pn_Cmp_Leg: /* odered */
+ sse_pnc = 7;
+ break;
+ case pn_Cmp_Uo: /* unordered */
+ sse_pnc = 3;
+ break;
+ case pn_Cmp_Ue: /* == */
+ sse_pnc = 0;
+ break;
+ case pn_Cmp_Ul: /* < */
+ sse_pnc = 1;
+ break;
+ case pn_Cmp_Ule: /* <= */
+ sse_pnc = 2;
+ break;
+ case pn_Cmp_Ug: /* > */
+ sse_pnc = 6;
+ break;
+ case pn_Cmp_Uge: /* >= */
+ sse_pnc = 5;
+ break;
+ case pn_Cmp_Ne: /* != */
+ sse_pnc = 4;
+ break;
+ }
+
+ assert(sse_pnc >= 0 && "unsupported floating point compare");
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
+ IA32_DO_EMIT(irn);
+}
+