+static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
+ switch(get_mode_size_bits(mode)) {
+ case 8:
+ return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
+ case 16:
+ return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
+ default:
+ return (char *)arch_register_get_name(reg);
+ }
+}
+
+/**
+ * Emits registers and/or address mode of a binary operation.
+ */
+const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
+ static char *buf = NULL;
+
+ /* verify that this function is never called on non-AM supporting operations */
+ //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
+
+#define PRODUCES_RESULT(n) \
+ (!(is_ia32_St(n) || \
+ is_ia32_Store8Bit(n) || \
+ is_ia32_CondJmp(n) || \
+ is_ia32_xCondJmp(n) || \
+ is_ia32_CmpSet(n) || \
+ is_ia32_xCmpSet(n) || \
+ is_ia32_SwitchJmp(n)))
+
+ if (! buf) {
+ buf = xcalloc(1, SNPRINTF_BUF_LEN);
+ }
+ else {
+ memset(buf, 0, SNPRINTF_BUF_LEN);
+ }
+
+ switch(get_ia32_op_type(n)) {
+ case ia32_Normal:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+ }
+ else {
+ const arch_register_t *in1 = get_in_reg(n, 2);
+ const arch_register_t *in2 = get_in_reg(n, 3);
+ const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
+ const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
+
+ if (is_ia32_emit_cl(n)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
+ in_name = "cl";
+ }
+
+ snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
+ }
+ break;
+ case ia32_AddrModeS:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
+ }
+ else {
+ if (PRODUCES_RESULT(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
+ }
+ else {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
+ }
+ }
+ break;
+ case ia32_AddrModeD:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
+ ia32_emit_am(n, env),
+ is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
+ get_ia32_cnst(n)); /* tell the assembler to store it's address. */
+ }
+ else {
+ const arch_register_t *in1 = get_in_reg(n, 2);
+ ir_mode *mode = get_ia32_res_mode(n);
+ const char *in_name;
+
+ mode = mode ? mode : get_ia32_ls_mode(n);
+ in_name = ia32_get_reg_name_for_mode(env, mode, in1);
+
+ if (is_ia32_emit_cl(n)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
+ in_name = "cl";
+ }
+
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
+ }
+ break;
+ default:
+ assert(0 && "unsupported op type");
+ }
+
+#undef PRODUCES_RESULT
+
+ return buf;
+}
+
+/**
+ * Returns the xxx PTR string for a given mode
+ *
+ * @param mode the mode
+ * @param x87_insn if non-zero returns the string for a x87 instruction
+ * else for a SSE instruction
+ */
+static const char *pointer_size(ir_mode *mode, int x87_insn)
+{
+ if (mode) {
+ switch (get_mode_size_bits(mode)) {
+ case 8: return "BYTE PTR";
+ case 16: return "WORD PTR";
+ case 32: return "DWORD PTR";
+ case 64:
+ if (x87_insn)
+ return "QWORD PTR";
+ return NULL;
+ case 80:
+ case 96: return "XWORD PTR";
+ default: return NULL;
+ }
+ }
+ return NULL;
+}
+
+/**
+ * Emits registers and/or address mode of a binary operation.
+ */
+const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+ static char *buf = NULL;
+
+ /* verify that this function is never called on non-AM supporting operations */
+ //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
+
+ if (! buf) {
+ buf = xcalloc(1, SNPRINTF_BUF_LEN);
+ }
+ else {
+ memset(buf, 0, SNPRINTF_BUF_LEN);
+ }
+
+ switch(get_ia32_op_type(n)) {
+ case ia32_Normal:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ ir_mode *mode = get_ia32_ls_mode(n);
+ const char *p = pointer_size(mode, 1);
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
+ }
+ else {
+ ia32_attr_t *attr = get_ia32_attr(n);
+ const arch_register_t *in1 = attr->x87[0];
+ const arch_register_t *in2 = attr->x87[1];
+ const arch_register_t *out = attr->x87[2];
+ const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
+
+ snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
+ }
+ break;
+ case ia32_AddrModeS:
+ case ia32_AddrModeD:
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+ break;
+ default:
+ assert(0 && "unsupported op type");
+ }
+
+#undef PRODUCES_RESULT
+
+ return buf;
+}
+