+ if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
+#if 0
+ if(emit_env->isa->opt_arch == arch_athlon) {
+ // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
+ // it is often beneficial to use the 3 xor trick instead of an xchg
+ cmnt_buf[0] = 0;
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
+ IA32_DO_EMIT(irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
+ IA32_DO_EMIT(irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
+ } else {
+#endif
+ ia32_emit_cstring(env, "\txchg ");
+ ia32_emit_source_register(env, node, 1);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ ia32_emit_finish_line(env, node);
+#if 0
+ }
+#endif
+ } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ ia32_emit_cstring(env, "\tpxorq ");
+ ia32_emit_source_register(env, node, 1);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ ia32_emit_finish_line(env, NULL);
+
+ ia32_emit_cstring(env, "\tpxorq ");
+ ia32_emit_source_register(env, node, 0);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 1);
+ ia32_emit_finish_line(env, NULL);
+
+ ia32_emit_cstring(env, "\tpxorq ");
+ ia32_emit_source_register(env, node, 1);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_source_register(env, node, 0);
+ ia32_emit_finish_line(env, node);
+ } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ /* is a NOP */
+ } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
+ /* is a NOP */
+ }
+}
+
+/**
+ * Emits code for Constant loading.
+ */
+static void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
+ ir_mode *mode = get_irn_mode(node);
+ ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
+
+ if (imm_tp == ia32_ImmSymConst) {
+ ia32_emit_cstring(env, "\tmovl $");
+ ia32_emit_immediate(env, node);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_dest_register(env, node, 0);
+ } else {
+ tarval *tv = get_ia32_Immop_tarval(node);
+ assert(mode == mode_Iu);
+ /* beware: in some rare cases mode is mode_b which has no tarval_null() */
+ if (tarval_is_null(tv)) {
+ if (env->isa->opt_arch == arch_pentium_4) {
+ /* P4 prefers sub r, r, others xor r, r */
+ ia32_emit_cstring(env, "\tsubl ");
+ } else {
+ ia32_emit_cstring(env, "\txorl ");
+ }
+ ia32_emit_dest_register(env, node, 0);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_dest_register(env, node, 0);
+ } else {
+ ia32_emit_cstring(env, "\tmovl $");
+ ia32_emit_immediate(env, node);
+ ia32_emit_cstring(env, ", ");
+ ia32_emit_dest_register(env, node, 0);
+ }
+ }
+ ia32_emit_finish_line(env, node);