+ /* we might need more space in the input arrays */
+ if (n_ins >= in_size) {
+ in_size *= 2;
+ const arch_register_req_t **new_in_reg_reqs
+ = OALLOCN(obst, const arch_register_req_t*,
+ in_size);
+ memcpy(new_in_reg_reqs, in_reg_reqs,
+ n_ins*sizeof(new_in_reg_reqs[0]));
+ ir_node **new_in = ALLOCANZ(ir_node*, in_size);
+ memcpy(new_in, in, n_ins*sizeof(new_in[0]));
+
+ in_reg_reqs = new_in_reg_reqs;
+ in = new_in;
+ }
+
+ /* add a new (dummy) input which occupies the register */
+ assert(outreq->type & arch_register_req_type_limited);
+ in_reg_reqs[n_ins] = outreq;
+ in[n_ins] = new_bd_ia32_ProduceVal(NULL, block);
+ ++n_ins;
+ }
+ } else {
+ bitset_t *used_outs = bitset_alloca(out_arity);
+ size_t orig_out_arity = out_arity;
+ for (int i = 0; i < n_inputs; ++i) {
+ const arch_register_req_t *inreq = in_reg_reqs[i];
+
+ if (inreq->cls == NULL)
+ continue;
+
+ size_t o;
+ for (o = 0; o < orig_out_arity; ++o) {
+ const arch_register_req_t *outreq;
+ if (bitset_is_set(used_outs, o))
+ continue;
+ outreq = out_reg_reqs[o];
+ if (!can_match(outreq, inreq))
+ continue;
+ bitset_set(used_outs, i);
+ break;
+ }
+ /* did we find any match? */
+ if (o < orig_out_arity)
+ continue;
+
+ /* we might need more space in the output arrays */
+ if (out_arity >= out_size) {
+ const arch_register_req_t **new_out_reg_reqs;
+
+ out_size *= 2;
+ new_out_reg_reqs
+ = OALLOCN(obst, const arch_register_req_t*, out_size);
+ memcpy(new_out_reg_reqs, out_reg_reqs,
+ out_arity * sizeof(new_out_reg_reqs[0]));
+ out_reg_reqs = new_out_reg_reqs;
+ }
+
+ /* add a new (dummy) output which occupies the register */
+ assert(inreq->type & arch_register_req_type_limited);
+ out_reg_reqs[out_arity] = inreq;
+ ++out_arity;
+ }
+ }
+
+ /* append none register requirement for the memory output */
+ if (out_arity + 1 >= out_size) {
+ const arch_register_req_t **new_out_reg_reqs;
+
+ out_size = out_arity + 1;
+ new_out_reg_reqs
+ = OALLOCN(obst, const arch_register_req_t*, out_size);
+ memcpy(new_out_reg_reqs, out_reg_reqs,
+ out_arity * sizeof(new_out_reg_reqs[0]));
+ out_reg_reqs = new_out_reg_reqs;
+ }
+
+ /* add a new (dummy) output which occupies the register */
+ out_reg_reqs[out_arity] = arch_no_register_req;
+ ++out_arity;
+
+ ir_node *new_node = new_bd_ia32_Asm(dbgi, new_block, n_ins, in, out_arity,
+ get_ASM_text(node), register_map);
+
+ backend_info_t *info = be_get_info(new_node);
+ for (size_t o = 0; o < out_arity; ++o) {
+ info->out_infos[o].req = out_reg_reqs[o];
+ }
+ arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
+
+ SET_IA32_ORIG_NODE(new_node, node);