-/**
- * Bitmask for the backend optimization settings.
- */
-enum ia32_optimize_t {
- IA32_OPT_INCDEC = 1 << 0, /**< optimize add/sub 1/-1 to inc/dec */
- IA32_OPT_CC = 1 << 1,
-};
-
-/**
- * Architectures. Clustered for easier macro implementation,
- * do not change.
- */
-enum cpu_support {
- arch_i386,
- arch_i486,
- arch_pentium,
- arch_pentium_pro,
- arch_pentium_mmx,
- arch_pentium_2,
- arch_pentium_3,
- arch_pentium_4,
- arch_pentium_m,
- arch_core,
- arch_k6,
- arch_athlon,
- arch_athlon_xp,
- arch_athlon_64,
- arch_opteron,
- arch_generic
-};
-
-/** checks for l <= x <= h */
-#define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
-
-/** returns true if it's Intel architecture */
-#define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
-
-/** returns true if it's AMD architecture */
-#define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
-
-/** return true if it's a Athlon/Opteron */
-#define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron)
-
-/** return true if the CPU has MMX support */
-#define ARCH_MMX(x) _IN_RANGE((x), arch_pentium_mmx, arch_opteron)
-
-#define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
- _IN_RANGE((x), arch_athlon, arch_opteron))
-
-/** floating point support */
-enum fp_support {
- fp_none, /**< no floating point instructions are used */
- fp_x87, /**< use x87 instructions */
- fp_sse2 /**< use SSE2 instructions */
-};
-
-/** Returns non-zero if the current floating point architecture is SSE2. */
-#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
-
-/** Returns non-zero if the current floating point architecture is x87. */
-#define USE_x87(cg) ((cg)->fp_kind == fp_x87)
-