* Implements a list scheduler for the MRIS algorithm in:
* Govindarajan, Yang, Amaral, Zhang, Gao
* Minimum Register Instruction Sequencing to Reduce Register Spills
* in out-of-order issue superscalar architectures
* Implements a list scheduler for the MRIS algorithm in:
* Govindarajan, Yang, Amaral, Zhang, Gao
* Minimum Register Instruction Sequencing to Reduce Register Spills
* in out-of-order issue superscalar architectures