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added get_next_ir_opcodes() to allow allocation of cosecutive opcodes
[libfirm]
/
ir
/
be
/
benode_t.h
diff --git
a/ir/be/benode_t.h
b/ir/be/benode_t.h
index
55bb360
..
a0e6ac4
100644
(file)
--- a/
ir/be/benode_t.h
+++ b/
ir/be/benode_t.h
@@
-17,12
+17,11
@@
#include "irmode.h"
#include "irnode.h"
#include "irmode.h"
#include "irnode.h"
+#include "entity_t.h"
#include "be_t.h"
#include "bearch.h"
#include "be_t.h"
#include "bearch.h"
-#define BE_SPILL_NO_OFFSET ((unsigned) -1)
-
typedef enum {
beo_NoBeOp = 0,
beo_Spill,
typedef enum {
beo_NoBeOp = 0,
beo_Spill,
@@
-52,8
+51,8
@@
int be_is_Copy(const ir_node *irn);
int be_is_Perm(const ir_node *irn);
int be_is_Keep(const ir_node *irn);
int be_is_Perm(const ir_node *irn);
int be_is_Keep(const ir_node *irn);
-void
be_set_Spill_offset(ir_node *irn, unsigned offse
t);
-
unsigned be_get_spill_offset
(ir_node *irn);
+void
be_set_Spill_entity(ir_node *irn, entity *en
t);
+
entity *be_get_spill_entity
(ir_node *irn);
ir_node *be_get_Spill_context(const ir_node *irn);
ir_node *be_get_Spill_context(const ir_node *irn);
@@
-63,8
+62,12
@@
ir_node *be_get_Spill_context(const ir_node *irn);
* This function incur register constraints to an output value of a Perm.
* This is used when handling register constraints in general,
* see beconstrperm.c
* This function incur register constraints to an output value of a Perm.
* This is used when handling register constraints in general,
* see beconstrperm.c
+ * @param irn The perm node.
+ * @param pos The position.
+ * @param req The requirements to set to.
+ * @param negate_limited When the requirements are limited, inverse the set of admissible registers.
*/
*/
-void be_set_Perm_out_req(ir_node *irn, int pos, const arch_register_req_t *req);
+void be_set_Perm_out_req(ir_node *irn, int pos, const arch_register_req_t *req
, unsigned negate_limited
);
/**
* Insert a Perm node after a specific node in the schedule.
/**
* Insert a Perm node after a specific node in the schedule.