+ be_do_stat_nodes(irg, "03 Prepare");
+
+ /*
+ * Since the code generator made a lot of new nodes and skipped
+ * a lot of old ones, we should do dead node elimination here.
+ * Note that this requires disabling the edges here.
+ */
+ edges_deactivate(irg);
+ //dead_node_elimination(irg);
+ edges_activate(irg);
+
+ /* Compute loop nesting information (for weighting copies) */
+ construct_cf_backedges(irg);
+ dump(DUMP_PREPARED, irg, "-prepared", dump_ir_block_graph);
+ BE_TIMER_ONLY(num_nodes_r = get_num_reachable_nodes(irg));
+
+ /* let backend prepare scheduling */
+ BE_TIMER_PUSH(t_codegen);
+ arch_code_generator_before_sched(birg.cg);
+ BE_TIMER_POP(t_codegen);
+
+ /* schedule the irg */
+ BE_TIMER_PUSH(t_sched);
+ list_sched(&birg, &be_options);
+ BE_TIMER_POP(t_sched);
+
+ dump(DUMP_SCHED, irg, "-sched", dump_ir_block_graph_sched);
+
+ /* check schedule */
+ BE_TIMER_PUSH(t_verify);
+ be_sched_vrfy(birg.irg, vrfy_option);
+ BE_TIMER_POP(t_verify);
+
+ be_do_stat_nodes(irg, "04 Schedule");
+
+ /* introduce patterns to assure constraints */
+ BE_TIMER_PUSH(t_constr);
+ /* we switch off optimizations here, because they might cause trouble */
+ save_optimization_state(&state);
+ set_optimize(0);
+ set_opt_normalize(0);
+
+ /* add Keeps for should_be_different constrained nodes */
+ /* beware: needs schedule due to usage of be_ssa_constr */
+ assure_constraints(&birg);
+ BE_TIMER_POP(t_constr);
+
+ dump(DUMP_SCHED, irg, "-assured", dump_ir_block_graph_sched);
+ be_do_stat_nodes(irg, "05 Constraints");
+
+ /* connect all stack modifying nodes together (see beabi.c) */
+ BE_TIMER_PUSH(t_abi);
+ be_abi_fix_stack_nodes(birg.abi, NULL);
+ BE_TIMER_POP(t_abi);
+
+ dump(DUMP_SCHED, irg, "-fix_stack", dump_ir_block_graph_sched);
+
+ /* check schedule */
+ BE_TIMER_PUSH(t_verify);
+ be_sched_vrfy(birg.irg, vrfy_option);
+ BE_TIMER_POP(t_verify);
+
+ /* do some statistics */
+ be_do_stat_reg_pressure(&birg);
+
+ /* stuff needs to be done after scheduling but before register allocation */
+ BE_TIMER_PUSH(t_codegen);
+ arch_code_generator_before_ra(birg.cg);
+ BE_TIMER_POP(t_codegen);
+
+ /* Do register allocation */
+ BE_TIMER_ONLY(lc_timer_start(t_regalloc));
+ ra_timer = ra->allocate(&birg);
+ BE_TIMER_ONLY(lc_timer_stop(t_regalloc));
+
+ dump(DUMP_RA, irg, "-ra", dump_ir_block_graph_sched);
+ be_do_stat_nodes(irg, "06 Register Allocation");
+
+ /* let the codegenerator prepare the graph for emitter */
+ BE_TIMER_PUSH(t_finish);
+ arch_code_generator_after_ra(birg.cg);
+ BE_TIMER_POP(t_finish);
+
+ /* fix stack offsets */
+ BE_TIMER_PUSH(t_abi);
+ be_abi_fix_stack_bias(birg.abi);
+ BE_TIMER_POP(t_abi);
+
+ BE_TIMER_PUSH(t_finish);
+ arch_code_generator_finish(birg.cg);
+ BE_TIMER_POP(t_finish);
+
+ dump(DUMP_FINAL, irg, "-finish", dump_ir_block_graph_sched);
+
+ /* check schedule and register allocation */
+ BE_TIMER_PUSH(t_verify);
+ if (vrfy_option == BE_VRFY_WARN) {
+ //irg_verify(birg.irg, VRFY_ENFORCE_SSA);
+ be_check_dominance(birg.irg);
+ be_verify_schedule(birg.irg);
+ be_verify_register_allocation(env.arch_env, birg.irg);
+ }
+ else if (vrfy_option == BE_VRFY_ASSERT) {
+ //assert(irg_verify(birg.irg, VRFY_ENFORCE_SSA) && "irg verification failed");
+ assert(be_check_dominance(birg.irg) && "Dominance verification failed");
+ assert(be_verify_schedule(birg.irg) && "Schedule verification failed");
+ assert(be_verify_register_allocation(env.arch_env, birg.irg)
+ && "register allocation verification failed");
+ }
+ BE_TIMER_POP(t_verify);
+
+ /* emit assembler code */
+ BE_TIMER_PUSH(t_emit);
+ arch_code_generator_done(birg.cg);
+ BE_TIMER_POP(t_emit);
+
+ dump(DUMP_FINAL, irg, "-end", dump_ir_extblock_graph_sched);
+
+ BE_TIMER_PUSH(t_abi);
+ be_abi_free(birg.abi);
+ BE_TIMER_POP(t_abi);
+
+ be_do_stat_nodes(irg, "07 Final");
+ restore_optimization_state(&state);
+
+ BE_TIMER_ONLY(num_nodes_a = get_num_reachable_nodes(irg));
+ BE_TIMER_POP(t_other);
+
+#define LC_EMIT(timer) printf("%-20s: %.3lf msec\n", lc_timer_get_description(timer), (double)lc_timer_elapsed_usec(timer) / 1000.0)
+#define LC_EMIT_RA(timer) printf("\t%-20s: %.3lf msec\n", lc_timer_get_description(timer), (double)lc_timer_elapsed_usec(timer) / 1000.0)
+ if (be_options.timing == BE_TIME_ON) {
+ printf("==>> IRG %s <<==\n", get_entity_name(get_irg_entity(irg)));
+ printf("# nodes at begin: %u\n", num_nodes_b);
+ printf("# nodes before ra: %u\n", num_nodes_r);
+ printf("# nodes at end: %u\n\n", num_nodes_a);
+ LC_EMIT(t_prolog);
+ LC_EMIT(t_abi);
+ LC_EMIT(t_codegen);
+ LC_EMIT(t_sched);
+ LC_EMIT(t_constr);
+ LC_EMIT(t_regalloc);
+ LC_EMIT_RA(ra_timer->t_prolog);
+ LC_EMIT_RA(ra_timer->t_live);
+ LC_EMIT_RA(ra_timer->t_spill);
+ LC_EMIT_RA(ra_timer->t_spillslots);
+ LC_EMIT_RA(ra_timer->t_color);
+ LC_EMIT_RA(ra_timer->t_ifg);
+ LC_EMIT_RA(ra_timer->t_copymin);
+ LC_EMIT_RA(ra_timer->t_ssa);
+ LC_EMIT_RA(ra_timer->t_epilog);
+ LC_EMIT_RA(ra_timer->t_verify);
+ LC_EMIT_RA(ra_timer->t_other);
+ LC_EMIT(t_finish);
+ LC_EMIT(t_emit);
+ LC_EMIT(t_verify);
+ LC_EMIT(t_other);
+ }
+#undef LC_EMIT