+ if(be_options.dump_flags & mask)
+ be_dump(irg, suffix, dumper);
+}
+
+/**
+ * Prepare a backend graph for code generation and initialize its birg
+ */
+static void initialize_birg(be_irg_t *birg, ir_graph *irg, be_main_env_t *env)
+{
+ memset(birg, 0, sizeof(*birg));
+ birg->irg = irg;
+ birg->main_env = env;
+
+ edges_deactivate_kind(irg, EDGE_KIND_DEP);
+ edges_activate_kind(irg, EDGE_KIND_DEP);
+
+ DBG((env->dbg, LEVEL_2, "====> IRG: %F\n", irg));
+ dump(DUMP_INITIAL, irg, "-begin", dump_ir_block_graph);
+
+ be_stat_init_irg(env->arch_env, irg);
+ be_do_stat_nodes(irg, "01 Begin");
+
+ /* set the current graph (this is important for several firm functions) */
+ current_ir_graph = irg;
+
+ /* Normalize proj nodes. */
+ normalize_proj_nodes(irg);
+
+ /* Make just one return node. */
+ normalize_one_return(irg);
+
+ /* Remove critical edges */
+ remove_critical_cf_edges(irg);
+
+ /* Ensure, that the ir_edges are computed. */
+ edges_assure(irg);
+
+ /* reset the phi handler. */
+ be_phi_handler_reset(env->phi_handler);
+
+ set_irg_phase_state(irg, phase_backend);
+}
+
+#ifdef WITH_LIBCORE
+
+#define BE_TIMER_PUSH(timer) \
+ if (be_options.timing == BE_TIME_ON) { \
+ int res = lc_timer_push(timer); \
+ if (be_options.vrfy_option == BE_VRFY_ASSERT) \
+ assert(res && "Timer already on stack, cannot be pushed twice."); \
+ else if (be_options.vrfy_option == BE_VRFY_WARN && ! res) \
+ fprintf(stderr, "Timer %s already on stack, cannot be pushed twice.\n", \
+ lc_timer_get_name(timer)); \
+ }
+#define BE_TIMER_POP(timer) \
+ if (be_options.timing == BE_TIME_ON) { \
+ lc_timer_t *tmp = lc_timer_pop(); \
+ if (be_options.vrfy_option == BE_VRFY_ASSERT) \
+ assert(tmp == timer && "Attempt to pop wrong timer."); \
+ else if (be_options.vrfy_option == BE_VRFY_WARN && tmp != timer) \
+ fprintf(stderr, "Attempt to pop wrong timer. %s is on stack, trying to pop %s.\n", \
+ lc_timer_get_name(tmp), lc_timer_get_name(timer)); \
+ timer = tmp; \
+ }
+
+#define BE_TIMER_ONLY(code) do { if (be_options.timing == BE_TIME_ON) { code; } } while(0)
+
+#else
+
+#define BE_TIMER_PUSH(timer)
+#define BE_TIMER_POP(timer)
+#define BE_TIMER_ONLY(code)
+
+#endif /* WITH_LIBCORE */
+
+
+/**
+ * The Firm backend main loop.
+ * Do architecture specific lowering for all graphs
+ * and call the architecture specific code generator.
+ *
+ * @param file_handle the file handle the output will be written to
+ * @param cup_name name of the compilation unit
+ */
+static void be_main_loop(FILE *file_handle, const char *cup_name)
+{
+ int i;
+ arch_isa_t *isa;
+ be_main_env_t env;
+ unsigned num_nodes_b = 0;
+ unsigned num_nodes_a = 0;
+ unsigned num_nodes_r = 0;
+ char prof_filename[256];
+ static const char suffix[] = ".prof";
+ be_irg_t *birgs;
+ unsigned num_birgs;
+ ir_graph **irg_list, **backend_irg_list;
+
+ be_ra_timer_t *ra_timer;
+
+#ifdef WITH_LIBCORE
+ lc_timer_t *t_abi = NULL;
+ lc_timer_t *t_codegen = NULL;
+ lc_timer_t *t_sched = NULL;
+ lc_timer_t *t_constr = NULL;
+ lc_timer_t *t_regalloc = NULL;
+ lc_timer_t *t_finish = NULL;
+ lc_timer_t *t_emit = NULL;
+ lc_timer_t *t_other = NULL;
+ lc_timer_t *t_verify = NULL;
+
+ if (be_options.timing == BE_TIME_ON) {
+ t_abi = lc_timer_register("beabi", "be abi introduction");
+ t_codegen = lc_timer_register("codegen", "codegeneration");
+ t_sched = lc_timer_register("sched", "scheduling");
+ t_constr = lc_timer_register("constr", "assure constraints");
+ t_regalloc = lc_timer_register("regalloc", "register allocation");
+ t_finish = lc_timer_register("finish", "graph finish");
+ t_emit = lc_timer_register("emiter", "code emiter");
+ t_verify = lc_timer_register("verify", "graph verification");
+ t_other = lc_timer_register("other", "other");
+ }
+#endif /* WITH_LIBCORE */
+
+ be_init_env(&env, file_handle);
+
+ isa = arch_env_get_isa(env.arch_env);
+
+ be_dbg_so(env.db_handle, cup_name);
+ be_dbg_types(env.db_handle);
+
+ /* backend may provide an ordered list of irgs where code should be generated for */
+ irg_list = NEW_ARR_F(ir_graph *, 0);
+ backend_irg_list = arch_isa_get_backend_irg_list(isa, &irg_list);
+
+ /* we might need 1 birg more for instrumentation constructor */
+ num_birgs = backend_irg_list ? ARR_LEN(backend_irg_list) : get_irp_n_irgs();
+ birgs = alloca(sizeof(birgs[0]) * (num_birgs + 1));
+
+ /* First: initialize all birgs */
+ for(i = 0; i < num_birgs; ++i) {
+ ir_graph *irg = backend_irg_list ? backend_irg_list[i] : get_irp_irg(i);
+ initialize_birg(&birgs[i], irg, &env);
+ }
+ DEL_ARR_F(irg_list);
+
+ /*
+ Get the filename for the profiling data.
+ Beware: '\0' is already included in sizeof(suffix)
+ */
+ memset(prof_filename, 0, sizeof(prof_filename));
+ strncpy(prof_filename, cup_name, sizeof(prof_filename) - sizeof(suffix));
+ strcat(prof_filename, suffix);
+
+ /*
+ Next: Either instruments all irgs with profiling code
+ or try to read in profile data for current translation unit.
+ */
+ if (be_options.opt_profile) {
+ ir_graph *prof_init_irg = be_profile_instrument(prof_filename, profile_default);
+ initialize_birg(&birgs[num_birgs], prof_init_irg, &env);
+ num_birgs++;
+ set_method_img_section(get_irg_entity(prof_init_irg), section_constructors);
+ }
+ else {
+ be_profile_read(prof_filename);
+ }
+
+ /* For all graphs */
+ for (i = 0; i < num_birgs; ++i) {
+ be_irg_t *birg = &birgs[i];
+ ir_graph *irg = birg->irg;
+ optimization_state_t state;
+ const arch_code_generator_if_t *cg_if;
+ char irg_name[128];
+
+ /* set the current graph (this is important for several firm functions) */
+ current_ir_graph = irg;
+
+#ifdef FIRM_STATISTICS
+ if(be_stat_ev_is_active()) {
+ ir_snprintf(irg_name, sizeof(irg_name), "%F", irg);
+ be_stat_tags[STAT_TAG_CLS] = "<all>";
+ be_stat_tags[STAT_TAG_IRG] = irg_name;
+ be_stat_ev_push(be_stat_tags, STAT_TAG_LAST, be_stat_file);
+ }
+#endif
+
+ /* stop and reset timers */
+ BE_TIMER_ONLY(
+ LC_STOP_AND_RESET_TIMER(t_abi);
+ LC_STOP_AND_RESET_TIMER(t_codegen);
+ LC_STOP_AND_RESET_TIMER(t_sched);
+ LC_STOP_AND_RESET_TIMER(t_constr);
+ LC_STOP_AND_RESET_TIMER(t_regalloc);
+ LC_STOP_AND_RESET_TIMER(t_finish);
+ LC_STOP_AND_RESET_TIMER(t_emit);
+ LC_STOP_AND_RESET_TIMER(t_verify);
+ LC_STOP_AND_RESET_TIMER(t_other);
+ );
+ BE_TIMER_PUSH(t_other); /* t_other */
+
+ /* Verify the initial graph */
+ BE_TIMER_PUSH(t_verify);
+ if (be_options.vrfy_option == BE_VRFY_WARN) {
+ irg_verify(irg, VRFY_ENFORCE_SSA);
+ be_check_dominance(irg);
+ } else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
+ assert(be_check_dominance(irg) && "Dominance verification failed");
+ }
+ BE_TIMER_POP(t_verify);
+
+ BE_TIMER_ONLY(num_nodes_b = get_num_reachable_nodes(irg));
+
+ /* Get the code generator interface. */
+ cg_if = isa->impl->get_code_generator_if(isa);
+
+ /* get a code generator for this graph. */
+ birg->cg = cg_if->init(birg);
+
+ /* some transformations need to be done before abi introduce */
+ arch_code_generator_before_abi(birg->cg);
+
+ /* reset the phi handler. */
+ be_phi_handler_reset(env.phi_handler);
+
+ /* implement the ABI conventions. */
+ BE_TIMER_PUSH(t_abi);
+ birg->abi = be_abi_introduce(birg);
+ BE_TIMER_POP(t_abi);
+
+ dump(DUMP_ABI, irg, "-abi", dump_ir_block_graph);
+ be_do_stat_nodes(irg, "02 Abi");
+
+ if (be_options.vrfy_option == BE_VRFY_WARN) {
+ be_check_dominance(irg);
+ be_verify_out_edges(irg);
+ }
+ else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(be_verify_out_edges(irg));
+ assert(be_check_dominance(irg) && "Dominance verification failed");
+ }
+
+ /* generate code */
+ BE_TIMER_PUSH(t_codegen);
+ arch_code_generator_prepare_graph(birg->cg);
+ BE_TIMER_POP(t_codegen);
+
+ be_do_stat_nodes(irg, "03 Prepare");
+
+ /* Transformation may produce nodes only reachable via out edges, kill them. */
+ be_kill_dead_nodes(irg);
+ dump(DUMP_PREPARED, irg, "-prepared", dump_ir_block_graph);
+ BE_TIMER_ONLY(num_nodes_r = get_num_reachable_nodes(irg));
+
+ if (be_options.vrfy_option == BE_VRFY_WARN) {
+ be_check_dominance(irg);
+ be_verify_out_edges(irg);
+ }
+ else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ assert(be_verify_out_edges(irg));
+ assert(be_check_dominance(irg) && "Dominance verification failed");
+ }
+
+ /**
+ * Create execution frequencies from profile data or estimate some
+ */
+ if (be_profile_has_data()) {
+ birg->exec_freq = be_create_execfreqs_from_profile(irg);
+ } else {
+ birg->exec_freq = compute_execfreq(irg, 10);
+ }
+
+ /* let backend prepare scheduling */
+ BE_TIMER_PUSH(t_codegen);
+ arch_code_generator_before_sched(birg->cg);
+ BE_TIMER_POP(t_codegen);
+
+ /* schedule the irg */
+ BE_TIMER_PUSH(t_sched);
+ switch (be_options.scheduler) {
+ default:
+ fprintf(stderr, "Warning: invalid scheduler (%d) selected, falling back to list scheduler.\n", be_options.scheduler);
+ case BE_SCHED_LIST:
+ list_sched(birg, &be_options);
+ break;
+#ifdef WITH_ILP
+ case BE_SCHED_ILP:
+ be_ilp_sched(birg);
+ //fprintf(stderr, "Warning: ILP scheduler not yet fully implemented, falling back to list scheduler.\n");
+ //list_sched(birg, &be_options);
+ break;
+#endif /* WITH_ILP */
+ };
+ BE_TIMER_POP(t_sched);
+
+ dump(DUMP_SCHED, irg, "-sched", dump_ir_block_graph_sched);
+
+ /* check schedule */
+ BE_TIMER_PUSH(t_verify);
+ be_sched_vrfy(irg, be_options.vrfy_option);
+ BE_TIMER_POP(t_verify);
+
+ be_do_stat_nodes(irg, "04 Schedule");
+
+ /* introduce patterns to assure constraints */
+ BE_TIMER_PUSH(t_constr);
+ /* we switch off optimizations here, because they might cause trouble */
+ save_optimization_state(&state);
+ set_optimize(0);
+ set_opt_normalize(0);
+
+ /* add Keeps for should_be_different constrained nodes */
+ /* beware: needs schedule due to usage of be_ssa_constr */
+ assure_constraints(birg);
+ BE_TIMER_POP(t_constr);
+
+ dump(DUMP_SCHED, irg, "-assured", dump_ir_block_graph_sched);
+ be_do_stat_nodes(irg, "05 Constraints");
+
+ /* connect all stack modifying nodes together (see beabi.c) */
+ BE_TIMER_PUSH(t_abi);
+ be_abi_fix_stack_nodes(birg->abi, NULL);
+ BE_TIMER_POP(t_abi);
+
+ dump(DUMP_SCHED, irg, "-fix_stack", dump_ir_block_graph_sched);
+
+ /* check schedule */
+ BE_TIMER_PUSH(t_verify);
+ be_sched_vrfy(irg, be_options.vrfy_option);
+ BE_TIMER_POP(t_verify);
+
+ /* do some statistics */
+ be_do_stat_reg_pressure(birg);
+
+ /* stuff needs to be done after scheduling but before register allocation */
+ BE_TIMER_PUSH(t_codegen);
+ arch_code_generator_before_ra(birg->cg);
+ BE_TIMER_POP(t_codegen);
+
+#ifdef FIRM_STATISTICS
+ if(be_stat_ev_is_active()) {
+ be_stat_ev_l("costs_before_ra",
+ (long) be_estimate_irg_costs(irg, env.arch_env, birg->exec_freq));
+ }
+#endif
+
+ /* Do register allocation */
+ BE_TIMER_PUSH(t_regalloc);
+ be_allocate_registers(birg);
+ BE_TIMER_POP(t_regalloc);
+
+#ifdef FIRM_STATISTICS
+ if(be_stat_ev_is_active()) {
+ be_stat_ev_l("costs_after_ra",
+ (long) be_estimate_irg_costs(irg, env.arch_env, birg->exec_freq));
+ }
+#endif
+
+ dump(DUMP_RA, irg, "-ra", dump_ir_block_graph_sched);
+ be_do_stat_nodes(irg, "06 Register Allocation");
+
+ /* let the code generator prepare the graph for emitter */
+ BE_TIMER_PUSH(t_finish);
+ arch_code_generator_after_ra(birg->cg);
+ BE_TIMER_POP(t_finish);
+
+ /* fix stack offsets */
+ BE_TIMER_PUSH(t_abi);
+ be_abi_fix_stack_nodes(birg->abi, NULL);
+ be_remove_dead_nodes_from_schedule(irg);
+ be_abi_fix_stack_bias(birg->abi);
+ BE_TIMER_POP(t_abi);
+
+ dump(DUMP_SCHED, irg, "-fix_stack_after_ra", dump_ir_block_graph_sched);
+
+ BE_TIMER_PUSH(t_finish);
+ arch_code_generator_finish(birg->cg);
+ BE_TIMER_POP(t_finish);
+
+ dump(DUMP_FINAL, irg, "-finish", dump_ir_block_graph_sched);
+
+ /* check schedule and register allocation */
+ BE_TIMER_PUSH(t_verify);
+ if (be_options.vrfy_option == BE_VRFY_WARN) {
+ //irg_verify(irg, VRFY_ENFORCE_SSA);
+ be_check_dominance(irg);
+ be_verify_out_edges(irg);
+ be_verify_schedule(irg);
+ be_verify_register_allocation(env.arch_env, irg);
+ }
+ else if (be_options.vrfy_option == BE_VRFY_ASSERT) {
+ //assert(irg_verify(irg, VRFY_ENFORCE_SSA) && "irg verification failed");
+ assert(be_verify_out_edges(irg));
+ assert(be_check_dominance(irg) && "Dominance verification failed");
+ assert(be_verify_schedule(irg) && "Schedule verification failed");
+ assert(be_verify_register_allocation(env.arch_env, irg)
+ && "register allocation verification failed");
+ }
+ BE_TIMER_POP(t_verify);
+
+ /* emit assembler code */
+ BE_TIMER_PUSH(t_emit);
+ arch_code_generator_done(birg->cg);
+ BE_TIMER_POP(t_emit);
+
+ dump(DUMP_FINAL, irg, "-end", dump_ir_block_graph_sched);
+
+ BE_TIMER_PUSH(t_abi);
+ be_abi_free(birg->abi);
+ BE_TIMER_POP(t_abi);
+
+ be_do_stat_nodes(irg, "07 Final");
+ restore_optimization_state(&state);
+
+ BE_TIMER_ONLY(num_nodes_a = get_num_reachable_nodes(irg));
+ BE_TIMER_POP(t_other);
+
+#define LC_EMIT(timer) \
+ if(!be_stat_ev_is_active()) { \
+ printf("%-20s: %.3lf msec\n", lc_timer_get_description(timer), (double)lc_timer_elapsed_usec(timer) / 1000.0); \
+ } else { \
+ be_stat_ev_l(lc_timer_get_name(timer), lc_timer_elapsed_msec(timer)); \
+ }
+#define LC_EMIT_RA(timer) \
+ if(!be_stat_ev_is_active()) { \
+ printf("\t%-20s: %.3lf msec\n", lc_timer_get_description(timer), (double)lc_timer_elapsed_usec(timer) / 1000.0); \
+ } else { \
+ be_stat_ev_l(lc_timer_get_name(timer), lc_timer_elapsed_msec(timer)); \
+ }
+ BE_TIMER_ONLY(
+ if(!be_stat_ev_is_active()) {
+ printf("==>> IRG %s <<==\n", get_entity_name(get_irg_entity(irg)));
+ printf("# nodes at begin: %u\n", num_nodes_b);
+ printf("# nodes before ra: %u\n", num_nodes_r);
+ printf("# nodes at end: %u\n\n", num_nodes_a);
+ }
+ LC_EMIT(t_abi);
+ LC_EMIT(t_codegen);
+ LC_EMIT(t_sched);
+ LC_EMIT(t_constr);
+ LC_EMIT(t_regalloc);
+ LC_EMIT_RA(ra_timer->t_prolog);
+ LC_EMIT_RA(ra_timer->t_live);
+ LC_EMIT_RA(ra_timer->t_spill);
+ LC_EMIT_RA(ra_timer->t_spillslots);
+ LC_EMIT_RA(ra_timer->t_color);
+ LC_EMIT_RA(ra_timer->t_ifg);
+ LC_EMIT_RA(ra_timer->t_copymin);
+ LC_EMIT_RA(ra_timer->t_ssa);
+ LC_EMIT_RA(ra_timer->t_epilog);
+ LC_EMIT_RA(ra_timer->t_verify);
+ LC_EMIT_RA(ra_timer->t_other);
+ LC_EMIT(t_finish);
+ LC_EMIT(t_emit);
+ LC_EMIT(t_verify);
+ LC_EMIT(t_other);
+ );
+#undef LC_EMIT_RA
+#undef LC_EMIT
+
+ be_free_birg(birg);
+
+ /* switched off due to statistics (statistic module needs all irgs) */
+#ifdef FIRM_STATISTICS
+ if (! stat_is_active())
+#endif
+ free_ir_graph(irg);
+
+ if(be_stat_ev_is_active()) {
+ be_stat_ev_pop();
+ }
+ }
+ be_profile_free();
+ be_done_env(&env);
+
+#undef BE_TIMER_POP
+#undef BE_TIMER_PUSH
+#undef BE_TIMER_ONLY