+ /* current type is not suitable */
+ if (tp_idx < 0)
+ continue;
+
+ a_idx = ILPVAR_IDX_DEAD(ba, na, tp_idx, t);
+ ARR_APP1(int, tmp_var_idx, na->ilp_vars.a[a_idx]);
+ }
+ /* do the same for livein nodes */
+ foreach_pset(ba->livein_nodes, livein) {
+ ir_node *irn = livein->irn;
+ be_ilpsched_irn_t *node = get_ilpsched_irn(env, irn);
+ int a_idx, tp_idx;
+
+ /* check if node can be alive here */
+ if (t >= livein->max_alive_steps)
+ continue;
+
+ tp_idx = is_valid_unit_type_for_node(cur_tp, node);
+
+ /* current type is not suitable */
+ if (tp_idx < 0)
+ continue;
+
+ a_idx = tp_idx * livein->max_alive_steps + t;
+ ARR_APP1(int, tmp_var_idx, livein->a[a_idx]);
+ }
+
+ if (ARR_LEN(tmp_var_idx) > 0)
+ lpp_set_factor_fast_bulk(lpp, cst, tmp_var_idx, ARR_LEN(tmp_var_idx), 1.0);
+ DEL_ARR_F(tmp_var_idx);
+
+ /* - num_nodes * y_{nt}^k */
+ y_idx = ILPVAR_IDX(cur_na, cur_tp_idx, t);
+ lpp_set_factor_fast(lpp, cst, cur_na->ilp_vars.y[y_idx], -1.0);
+ }
+ }
+ }
+ stat_ev_tim_pop("beilpsched_cst_pressure");
+}
+
+/**
+ * Create ILP branch constraints:
+ * Assure, alle nodes are scheduled prior to cfg op.
+ */
+static void create_branch_constraint(be_ilpsched_env_t *env, lpp_t *lpp, be_ilpsched_irn_t *block_node)
+{
+ char buf[1024];
+ ir_node *cur_irn, *cfop;
+ unsigned num_cst = 0;
+ unsigned num_non_branches = 0;
+ ilpsched_block_attr_t *ba = get_ilpsched_block_attr(block_node);
+
+ stat_ev_tim_push();
+ cfop = NULL;
+ /* determine number of non-branch nodes and the one and only branch node */
+ foreach_linked_irns(ba->head_ilp_nodes, cur_irn) {
+ switch (get_irn_opcode(cur_irn)) {
+ case iro_Phi:
+ case beo_Start:
+ case iro_End:
+ case iro_Proj:
+ case iro_Bad:
+ case iro_Unknown:
+ num_non_branches++;
+ break;
+ default:
+ if (is_cfop(cur_irn)) {
+ assert(cfop == NULL && "Highlander - there can be only one to be constrained");
+ cfop = cur_irn;
+ }
+ else {
+ num_non_branches++;
+ }
+ break;
+ }
+ }
+
+ if (cfop) {
+ be_ilpsched_irn_t *cf_node = get_ilpsched_irn(env, cfop);
+ ilpsched_node_attr_t *cf_na = get_ilpsched_node_attr(cf_node);
+ unsigned t;
+
+ /* for each time step */
+ for (t = cf_na->asap - 1; t <= cf_na->alap - 1; ++t) {
+ int *non_branch_vars, *branch_vars;
+ int cst;
+
+ snprintf(buf, sizeof(buf), "branch_cst_%u_n%u", t, get_irn_idx(cfop));
+ cst = lpp_add_cst_uniq(lpp, buf, lpp_greater, 0.0);
+ DBG((env->dbg, LEVEL_2, "added constraint %s\n", buf));
+ num_cst++;
+
+ /* sum(overall non branches: n)x_{nt}^k - sum(overall branches: b)(num_non_branches * x_{bt}^k >= 0) */
+ non_branch_vars = NEW_ARR_F(int, 0);
+ branch_vars = NEW_ARR_F(int, 0);
+ foreach_linked_irns(ba->head_ilp_nodes, cur_irn) {
+ be_ilpsched_irn_t *node = get_ilpsched_irn(env, cur_irn);
+ ilpsched_node_attr_t *na = get_ilpsched_node_attr(node);
+ int tp_idx;
+
+ if (cur_irn == cfop) {
+ /* for all unit types available for this node */
+ for (tp_idx = na->n_unit_types - 1; tp_idx >= 0; --tp_idx) {
+ unsigned idx = ILPVAR_IDX(na, tp_idx, t);
+ ARR_APP1(int, branch_vars, na->ilp_vars.x[idx]);