+/* Helpers */
+#define ASSERT_OU_AVAIL(co) assert((co)->units.next && "Representation as optimization-units not build")
+#define ASSERT_GS_AVAIL(co) assert((co)->nodes && "Representation as graph not build")
+
+#define get_irn_col(co, irn) arch_register_get_index(arch_get_irn_register((co)->aenv, irn))
+#define set_irn_col(co, irn, col) arch_set_irn_register((co)->aenv, irn, arch_register_for_index((co)->cls, col))
+#define is_curr_reg_class(co, irn) (arch_get_irn_reg_class((co)->aenv, irn, -1) == (co)->cls)
+
+#define list_entry_units(lh) list_entry(lh, unit_t, units)
+
+#define is_Reg_Phi(irn) (is_Phi(irn) && mode_is_data(get_irn_mode(irn)))
+
+#define get_Perm_src(irn) (get_irn_n(get_Proj_pred(irn), get_Proj_proj(irn)))
+#define is_Perm(arch_env, irn) (arch_irn_classify(arch_env, irn) == arch_irn_class_perm)
+#define is_Perm_Proj(arch_env, irn) (is_Proj(irn) && is_Perm(arch_env, get_Proj_pred(irn)))
+
+#define is_2addr_code(arch_env, irn, req) (arch_get_register_req(arch_env, req, irn, -1)->type == arch_register_req_type_should_be_same)
+
+
+
+/******************************************************************************
+ ____ _ _ _ _ _ _____ _
+ / __ \ | | | | | | (_) | / ____| |
+ | | | |_ __ | |_| | | |_ __ _| |_ ___ | (___ | |_ ___ _ __ __ _ __ _ ___
+ | | | | '_ \| __| | | | '_ \| | __/ __| \___ \| __/ _ \| '__/ _` |/ _` |/ _ \
+ | |__| | |_) | |_| |__| | | | | | |_\__ \ ____) | || (_) | | | (_| | (_| | __/
+ \____/| .__/ \__|\____/|_| |_|_|\__|___/ |_____/ \__\___/|_| \__,_|\__, |\___|
+ | | __/ |
+ |_| |___/
+ ******************************************************************************/
+
+#define MIS_HEUR_TRIGGER 8
+