-#define BE_TIMER_INIT(main_opts) be_init_timer(main_opts)
-
-#define BE_TIMER_PUSH(timer) \
- if (main_opts->timing == BE_TIME_ON) { \
- if (! lc_timer_push(timer)) { \
- if (options.vrfy_option == BE_CH_VRFY_ASSERT) \
- assert(!"Timer already on stack, cannot be pushed twice."); \
- else if (options.vrfy_option == BE_CH_VRFY_WARN) \
- fprintf(stderr, "Timer %s already on stack, cannot be pushed twice.\n", \
- lc_timer_get_name(timer)); \
- } \
- }
-#define BE_TIMER_POP(timer) \
- if (main_opts->timing == BE_TIME_ON) { \
- lc_timer_t *tmp = lc_timer_pop(); \
- if (options.vrfy_option == BE_CH_VRFY_ASSERT) \
- assert(tmp == timer && "Attempt to pop wrong timer."); \
- else if (options.vrfy_option == BE_CH_VRFY_WARN && tmp != timer) \
- fprintf(stderr, "Attempt to pop wrong timer. %s is on stack, trying to pop %s.\n", \
- lc_timer_get_name(tmp), lc_timer_get_name(timer)); \
- timer = tmp; \
- }
-#else
+/**
+ * Perform things which need to be done per register class after spilling.
+ */
+static void post_spill(post_spill_env_t *pse, int iteration) {
+ be_chordal_env_t *chordal_env = &pse->cenv;
+ be_irg_t *birg = pse->birg;
+ ir_graph *irg = birg->irg;
+ const be_main_env_t *main_env = birg->main_env;
+ int colors_n = arch_register_class_n_regs(chordal_env->cls);
+ int allocatable_regs = colors_n - be_put_ignore_regs(birg, chordal_env->cls, NULL);
+
+ /* some special classes contain only ignore regs, no work to be done */
+ if (allocatable_regs > 0) {
+ stat_ev_dbl("bechordal_spillcosts", be_estimate_irg_costs(irg, main_env->arch_env, birg->exec_freq) - pse->pre_spill_cost);
+
+ /*
+ If we have a backend provided spiller, post spill is
+ called in a loop after spilling for each register class.
+ But we only need to fix stack nodes once in this case.
+ */
+ BE_TIMER_PUSH(t_ra_spill_apply);
+ check_for_memory_operands(chordal_env);
+ if (iteration == 0) {
+ be_abi_fix_stack_nodes(birg->abi);
+ }
+ BE_TIMER_POP(t_ra_spill_apply);
+
+ BE_TIMER_PUSH(t_verify);
+
+ /* verify schedule and register pressure */
+ if (chordal_env->opts->vrfy_option == BE_CH_VRFY_WARN) {
+ be_verify_schedule(birg);
+ be_verify_register_pressure(birg, pse->cls, irg);
+ } else if (chordal_env->opts->vrfy_option == BE_CH_VRFY_ASSERT) {
+ assert(be_verify_schedule(birg) && "Schedule verification failed");
+ assert(be_verify_register_pressure(birg, pse->cls, irg)
+ && "Register pressure verification failed");
+ }
+ BE_TIMER_POP(t_verify);
+
+ /* Color the graph. */
+ BE_TIMER_PUSH(t_ra_color);
+ be_ra_chordal_color(chordal_env);
+ BE_TIMER_POP(t_ra_color);
+
+ dump(BE_CH_DUMP_CONSTR, irg, pse->cls, "-color", dump_ir_block_graph_sched);
+
+ /* Create the ifg with the selected flavor */
+ BE_TIMER_PUSH(t_ra_ifg);
+ chordal_env->ifg = be_create_ifg(chordal_env);
+ BE_TIMER_POP(t_ra_ifg);
+
+ stat_ev_if {
+ be_ifg_stat_t stat;
+ be_node_stats_t node_stats;
+
+ be_ifg_stat(birg, chordal_env->ifg, &stat);
+ stat_ev_dbl("bechordal_ifg_nodes", stat.n_nodes);
+ stat_ev_dbl("bechordal_ifg_edges", stat.n_edges);
+ stat_ev_dbl("bechordal_ifg_comps", stat.n_comps);
+
+ be_collect_node_stats(&node_stats, birg);
+ be_subtract_node_stats(&node_stats, &last_node_stats);
+
+ stat_ev_dbl("bechordal_perms_before_coal",
+ node_stats[BE_STAT_PERMS]);
+ stat_ev_dbl("bechordal_copies_before_coal",
+ node_stats[BE_STAT_COPIES]);
+ }
+
+ /* copy minimization */
+ BE_TIMER_PUSH(t_ra_copymin);
+ co_driver(chordal_env);
+ BE_TIMER_POP(t_ra_copymin);