+ for(irn = sched_next(perm); is_Proj(irn); irn = sched_next(irn))
+ if(!try_pre_color(env, irn, pre_colored, colors_used))
+ pset_insert_ptr(leftover, irn);
+
+ cnstr = irn;
+ last = irn;
+
+ if(get_irn_mode(cnstr) == mode_T) {
+ for(irn = sched_next(cnstr); is_Proj(irn); irn = sched_next(irn))
+ if(!try_pre_color(env, irn, pre_colored, colors_used))
+ pset_insert_ptr(leftover, irn);
+
+ last = sched_prev(irn);
+ }
+
+ else
+ try_pre_color(env, cnstr, pre_colored, colors_used);
+
+ pset_insert_pset_ptr(alloc_env->pre_colored, pre_colored);
+
+ for(irn = pset_first(leftover); irn; irn = pset_next(leftover)) {
+ const arch_register_t *reg;
+ ir_node *precol;
+ int colored = 0;
+
+ for(precol = pset_first(pre_colored); precol; precol = pset_next(pre_colored)) {
+ const arch_register_t *pre_col_reg = arch_get_irn_register(arch_env, precol);
+
+ if(!values_interfere(irn, precol)) {
+ reg = arch_get_irn_register(arch_env, precol);
+ pset_break(pre_colored);
+ pset_remove_ptr(pre_colored, precol);
+ DBG((dbg, LEVEL_2, "non-interfering %+F setting to %s\n", irn, reg->name));
+ colored = 1;
+ break;
+ }
+ }
+
+ if(!colored) {
+ int col = bitset_next_clear(colors_used, 0);
+
+ assert(col >= 0 && col < env->cls->n_regs && "There must be a register left");
+ reg = arch_register_for_index(env->cls, col);
+
+ DBG((dbg, LEVEL_2, "coloring leftover %+F with %s\n", irn, reg->name));
+ }
+
+ arch_set_irn_register(arch_env, irn, reg);
+ pset_insert_ptr(alloc_env->pre_colored, irn);
+ bitset_set(colors_used, reg->index);
+ }
+
+ del_pset(leftover);
+ del_pset(pre_colored);
+
+ return last;
+}
+
+/**
+ * Handle constraint nodes in each basic block.
+ * be_insert_constr_perms() inserts Perm nodes which perm
+ * over all values live at the constrained node right in front
+ * of the constrained node. These Perms signal a constrained node.
+ * For further comments, refer to handle_constraints_at_perm().
+ */
+static void constraints(ir_node *bl, void *data)
+{
+ be_chordal_alloc_env_t *env = data;
+ arch_env_t *arch_env = env->chordal_env->main_env->arch_env;
+ ir_node *irn;
+
+ for(irn = sched_first(bl); !sched_is_end(irn); irn = sched_next(irn)) {
+ if(be_is_Perm(irn) && arch_irn_has_reg_class(arch_env, irn, 0, env->chordal_env->cls))
+ irn = handle_constraints_at_perm(env, irn);
+ }
+}
+
+/**
+ * Annotate the register pressure to the nodes and compute
+ * the liveness intervals.
+ * @param block The block to do it for.
+ * @param env_ptr The environment.
+ */
+static void pressure(ir_node *block, void *env_ptr)
+{
+/* Convenience macro for a def */
+#define border_def(irn, step, real) \
+ border_add(env, head, irn, step, pressure--, 1, real)
+
+/* Convenience macro for a use */
+#define border_use(irn, step, real) \
+ border_add(env, head, irn, step, ++pressure, 0, real)
+
+ be_chordal_alloc_env_t *alloc_env = env_ptr;
+ be_chordal_env_t *env = alloc_env->chordal_env;
+ bitset_t *live = alloc_env->live;
+ firm_dbg_module_t *dbg = env->dbg;
+ ir_node *irn;
+
+ int i, n;
+ unsigned step = 0;
+ unsigned pressure = 0;
+ struct list_head *head;
+ pset *live_in = put_live_in(block, pset_new_ptr_default());
+ pset *live_end = put_live_end(block, pset_new_ptr_default());