+static void pair_up_operands(const be_chordal_alloc_env_t *alloc_env, insn_t *insn)
+{
+ const be_chordal_env_t *env = alloc_env->chordal_env;
+
+ int n_uses = insn_n_uses(insn);
+ int n_defs = insn_n_defs(insn);
+ bitset_t *bs = bitset_alloca(env->cls->n_regs);
+ bipartite_t *bp = bipartite_new(n_defs, n_uses);
+ int *pairing = alloca(MAX(n_defs, n_uses) * sizeof(pairing[0]));
+
+ int i, j;
+
+ /*
+ For each out operand, try to find an in operand which can be assigned the
+ same register as the out operand.
+ */
+ for(j = 0; j < insn->use_start; ++j) {
+ operand_t *out_op = &insn->ops[j];
+
+ /* Try to find an in operand which has ... */
+ for(i = insn->use_start; i < insn->n_ops; ++i) {
+ const operand_t *op = &insn->ops[i];
+
+ /*
+ The in operand can only be paired with a def, if the node defining the
+ operand's value does not interfere with the instruction itself. That
+ would mean, that it is live at the instruction, so no result of the instruction
+ can have the same register as the operand.
+
+ Furthermore, tow operands can be paired, if the admissible registers
+ of one are a subset of the other's. We record the operand whose constraints
+ count in the decisive array.
+ */
+ if(!values_interfere(op->irn, op->carrier)) {
+ if(get_decisive_partner_regs(bs, out_op, op))
+ bipartite_add(bp, j, i - insn->use_start);
+ }
+ }
+ }
+
+ /* Compute the pairing. */
+ bipartite_matching(bp, pairing);
+ for(i = 0; i < insn->use_start; ++i) {
+ int p = pairing[i] + insn->use_start;
+
+ if(p >= insn->use_start) {
+ insn->ops[i].partner = &insn->ops[p];
+ insn->ops[p].partner = &insn->ops[i];
+ }
+ }
+
+ bipartite_free(bp);
+}
+
+
+static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env, insn_t **the_insn)
+{
+ be_chordal_env_t *env = alloc_env->chordal_env;
+ const arch_env_t *aenv = env->birg->main_env->arch_env;
+ firm_dbg_module_t *dbg = alloc_env->constr_dbg;
+ insn_t *insn = *the_insn;
+ ir_node *bl = get_nodes_block(insn->irn);
+ ir_node *copy = NULL;
+ ir_node *perm = NULL;
+ bitset_t *out_constr = bitset_alloca(env->cls->n_regs);
+ bitset_t *bs = bitset_alloca(env->cls->n_regs);
+
+ int i;
+
+ assert(insn->has_constraints && "only do this for constrained nodes");
+
+ /*
+ Collect all registers that occur in output constraints.
+ This is necessary, since if the insn has one of these as an input constraint
+ and the corresponding operand interferes with the insn, the operand must
+ be copied.
+ */
+ for(i = 0; i < insn->use_start; ++i) {
+ operand_t *op = &insn->ops[i];
+ if(op->has_constraints)
+ bitset_or(out_constr, op->regs);
+ }
+
+ /*
+ Now, figure out which input operand must be copied since it has input
+ constraints which are also output constraints.
+ */
+ for(i = insn->use_start; i < insn->n_ops; ++i) {
+ operand_t *op = &insn->ops[i];
+ if(op->has_constraints && (values_interfere(op->carrier, insn->irn) || arch_irn_is(aenv, op->carrier, ignore))) {
+ bitset_copy(bs, op->regs);
+ bitset_and(bs, out_constr);
+
+ /*
+ The operand (interfering with the node) has input constraints
+ which also occur as output constraints, so insert a copy.
+ */
+ if(bitset_popcnt(bs) > 0) {
+ copy = be_new_Copy(op->req.cls, env->irg, bl, op->carrier);
+ insn->ops[i].carrier = copy;
+ sched_add_before(insn->irn, copy);
+
+ DBG((dbg, LEVEL_2, "adding copy for interfering and constrained op %+F\n", op->carrier));
+ }
+ }
+ }
+
+ /*
+ Make the Perm, recompute liveness and re-scan the insn since the
+ in operands are now the Projs of the Perm.
+ */
+ perm = insert_Perm_after(aenv, env->cls, env->dom_front, sched_prev(insn->irn));
+
+ /* Registers are propagated by insert_Perm_after(). Clean them here! */
+ if(perm) {
+ const ir_edge_t *edge;
+
+ foreach_out_edge(perm, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ arch_set_irn_register(aenv, proj, NULL);
+ }