+ /*
+ Perms inserted before the constraint handling phase are considered to be
+ correctly precolored. These Perms arise during the ABI handling phase.
+ */
+ if(insn->has_constraints) {
+ const arch_env_t *aenv = env->birg->main_env->arch_env;
+ int n_regs = env->cls->n_regs;
+ bitset_t *bs = bitset_alloca(n_regs);
+ ir_node **alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
+ bipartite_t *bp = bipartite_new(n_regs, n_regs);
+ int *assignment = alloca(n_regs * sizeof(assignment[0]));
+ pmap *partners = pmap_create();
+ DEBUG_ONLY(firm_dbg_module_t *dbg = alloc_env->constr_dbg;)
+
+ int i, n_alloc;
+ long col;
+ const ir_edge_t *edge;
+ ir_node *perm = NULL;
+
+ /*
+ prepare the constraint handling of this node.
+ Perms are constructed and Copies are created for constrained values
+ interfering with the instruction.
+ */
+ perm = pre_process_constraints(alloc_env, &insn);
+
+ /* find suitable in operands to the out operands of the node. */
+ pair_up_operands(alloc_env, insn);
+
+ /*
+ look at the in/out operands and add each operand (and its possible partner)
+ to a bipartite graph (left: nodes with partners, right: admissible colors).
+ */
+ for(i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
+ be_operand_t *op = &insn->ops[i];
+
+ /*
+ If the operand has no partner or the partner has not been marked
+ for allocation, determine the admissible registers and mark it
+ for allocation by associating the node and its partner with the
+ set of admissible registers via a bipartite graph.
+ */
+ if(!op->partner || !pmap_contains(partners, op->partner->carrier)) {
+
+ pmap_insert(partners, op->carrier, op->partner ? op->partner->carrier : NULL);
+ alloc_nodes[n_alloc] = op->carrier;
+
+ DBG((dbg, LEVEL_2, "\tassociating %+F and %+F\n", op->carrier, op->partner ? op->partner->carrier : NULL));
+
+ bitset_clear_all(bs);
+ get_decisive_partner_regs(bs, op, op->partner);
+
+ DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier, bs));
+
+ bitset_foreach(bs, col)
+ bipartite_add(bp, n_alloc, col);
+
+ n_alloc++;
+ }
+ }
+
+ /*
+ Put all nodes which live through the constrained instruction also to the
+ allocation bipartite graph. They are considered unconstrained.
+ */
+ if(perm) {
+ foreach_out_edge(perm, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+
+ assert(is_Proj(proj));
+
+ if(values_interfere(env->lv, proj, irn) && !pmap_contains(partners, proj)) {
+ assert(n_alloc < n_regs);
+ alloc_nodes[n_alloc] = proj;
+ pmap_insert(partners, proj, NULL);
+
+ bitset_clear_all(bs);
+ arch_put_non_ignore_regs(aenv, env->cls, bs);
+ bitset_andnot(bs, env->ignore_colors);
+ bitset_foreach(bs, col)
+ bipartite_add(bp, n_alloc, col);
+
+ n_alloc++;
+ }
+ }
+ }
+
+ /* Compute a valid register allocation. */
+ bipartite_matching(bp, assignment);
+
+ /* Assign colors obtained from the matching. */
+ for(i = 0; i < n_alloc; ++i) {
+ const arch_register_t *reg;
+ ir_node *nodes[2];
+ int j;
+
+ assert(assignment[i] >= 0 && "there must have been a register assigned");
+ reg = arch_register_for_index(env->cls, assignment[i]);
+
+ nodes[0] = alloc_nodes[i];
+ nodes[1] = pmap_get(partners, alloc_nodes[i]);
+
+ for(j = 0; j < 2; ++j) {
+ if(!nodes[j])
+ continue;
+
+ arch_set_irn_register(aenv, nodes[j], reg);
+ pset_hinsert_ptr(alloc_env->pre_colored, nodes[j]);
+ DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", nodes[j], reg->name));