- for(irn = pset_first(leftover); irn; irn = pset_next(leftover)) {
- const arch_register_t *reg;
- ir_node *precol;
- int colored = 0;
-
- for(precol = pset_first(pre_colored); precol; precol = pset_next(pre_colored)) {
- const arch_register_t *pre_col_reg = arch_get_irn_register(arch_env, precol);
-
- if(!values_interfere(irn, precol)) {
- reg = arch_get_irn_register(arch_env, precol);
- pset_break(pre_colored);
- pset_remove_ptr(pre_colored, precol);
- DBG((dbg, LEVEL_2, "non-interfering %+F setting to %s\n", irn, reg->name));
- colored = 1;
- break;
+ /*
+ If the current node is a barrier toggle the silent flag.
+ If we are in the start block, we are ought to be silent at the beginning,
+ so the toggling activates the constraint handling but skips the barrier.
+ If we are in the end block we handle the in requirements of the barrier
+ and set the rest to silent.
+ */
+ if(be_is_Barrier(irn))
+ *silent = !*silent;
+
+ if(be_silent)
+ goto end;
+
+ /*
+ Perms inserted before the constraint handling phase are considered to be
+ correctly precolored. These Perms arise during the ABI handling phase.
+ */
+ if(!insn->has_constraints)
+ goto end;
+
+ aenv = env->birg->main_env->arch_env;
+ n_regs = env->cls->n_regs;
+ bs = bitset_alloca(n_regs);
+ alloc_nodes = alloca(n_regs * sizeof(alloc_nodes[0]));
+ //bp = hungarian_new(n_regs, n_regs, 2, HUNGARIAN_MATCH_PERFECT);
+ bp = bipartite_new(n_regs, n_regs);
+ assignment = alloca(n_regs * sizeof(assignment[0]));
+ partners = pmap_create();
+
+ /*
+ prepare the constraint handling of this node.
+ Perms are constructed and Copies are created for constrained values
+ interfering with the instruction.
+ */
+ perm = pre_process_constraints(alloc_env, &insn);
+
+ /* find suitable in operands to the out operands of the node. */
+ pair_up_operands(alloc_env, insn);
+
+ /*
+ look at the in/out operands and add each operand (and its possible partner)
+ to a bipartite graph (left: nodes with partners, right: admissible colors).
+ */
+ for(i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
+ be_operand_t *op = &insn->ops[i];
+
+ /*
+ If the operand has no partner or the partner has not been marked
+ for allocation, determine the admissible registers and mark it
+ for allocation by associating the node and its partner with the
+ set of admissible registers via a bipartite graph.
+ */
+ if(!op->partner || !pmap_contains(partners, op->partner->carrier)) {
+ ir_node *partner = op->partner ? op->partner->carrier : NULL;
+ int i;
+
+ pmap_insert(partners, op->carrier, partner);
+ if(partner != NULL)
+ pmap_insert(partners, partner, op->carrier);
+
+ /* don't insert a node twice */
+ for(i = 0; i < n_alloc; ++i) {
+ if(alloc_nodes[i] == op->carrier) {
+ break;
+ }
+ }
+ if(i < n_alloc)
+ continue;
+
+ alloc_nodes[n_alloc] = op->carrier;
+
+ DBG((dbg, LEVEL_2, "\tassociating %+F and %+F\n", op->carrier,
+ partner));
+
+ bitset_clear_all(bs);
+ get_decisive_partner_regs(bs, op, op->partner);
+
+ DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier,
+ bs));
+
+ bitset_foreach(bs, col) {
+ //hungarian_add(bp, n_alloc, col, 1);
+ bipartite_add(bp, n_alloc, col);
+ }
+
+ n_alloc++;
+ }
+ }
+
+ /*
+ Put all nodes which live through the constrained instruction also to the
+ allocation bipartite graph. They are considered unconstrained.
+ */
+ if(perm != NULL) {
+ foreach_out_edge(perm, edge) {
+ int i;
+ ir_node *proj = get_edge_src_irn(edge);
+
+ assert(is_Proj(proj));
+
+ if(!values_interfere(birg, proj, irn) || pmap_contains(partners, proj))
+ continue;
+
+ /* don't insert a node twice */
+ for(i = 0; i < n_alloc; ++i) {
+ if(alloc_nodes[i] == proj) {
+ break;
+ }