+ be_operand_t *op = &insn->ops[i];
+ if(op->has_constraints)
+ bitset_or(out_constr, op->regs);
+ }
+
+ /*
+ Now, figure out which input operand must be copied since it has input
+ constraints which are also output constraints.
+ */
+ (void) bl;
+ (void) copy;
+ (void) bs;
+ (void) dbg;
+#if 0
+ for(i = insn->use_start; i < insn->n_ops; ++i) {
+ be_operand_t *op = &insn->ops[i];
+ if(op->has_constraints && (values_interfere(env->lv, op->carrier, insn->irn) || arch_irn_is(aenv, op->carrier, ignore))) {
+ bitset_copy(bs, op->regs);
+ bitset_and(bs, out_constr);
+
+ /*
+ The operand (interfering with the node) has input constraints
+ which also occur as output constraints, so insert a copy.
+ */
+ if(bitset_popcnt(bs) > 0) {
+ copy = be_new_Copy(op->req.cls, env->irg, bl, op->carrier);
+ op->carrier = copy;
+ sched_add_before(insn->irn, copy);
+ set_irn_n(insn->irn, op->pos, op->carrier);
+
+ DBG((dbg, LEVEL_2, "adding copy for interfering and constrained op %+F\n", op->carrier));
+ }
+ }
+ }
+#endif
+
+ /*
+ Make the Perm, recompute liveness and re-scan the insn since the
+ in operands are now the Projs of the Perm.
+ */
+ perm = insert_Perm_after(aenv, env->lv, env->cls, env->dom_front, sched_prev(insn->irn));
+
+ /* Registers are propagated by insert_Perm_after(). Clean them here! */
+ if(perm) {
+ const ir_edge_t *edge;
+
+ be_stat_ev("constr_perm", 1);
+ foreach_out_edge(perm, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ arch_set_irn_register(aenv, proj, NULL);
+ }