-* Put the registers to be ignored in this IRG into a bitset.
-* @param birg The backend IRG data structure.
-* @param cls The register class.
-* @param bs The bitset (may be NULL).
-* @return The number of registers to be ignored.
-*/
-int be_put_ignore_regs(const be_irg_t *birg, const arch_register_class_t *cls,
- bitset_t *bs);
+ * Initialize the backend. Must be run first in init_firm();
+ */
+void firm_be_init(void);
+void firm_be_finish(void);
+
+extern int be_timing;
+
+#define BE_TIMER_PUSH(timer) \
+ if (be_timing) { \
+ int res = ir_timer_push(timer); \
+ (void) res; \
+ assert(res && "Timer already on stack, cannot be pushed twice."); \
+ }
+
+#define BE_TIMER_POP(timer) \
+ if (be_timing) { \
+ ir_timer_t *tmp = ir_timer_pop(); \
+ (void) tmp; \
+ assert(tmp == timer && "Attempt to pop wrong timer."); \
+ }
+
+extern ir_timer_t *t_abi;
+extern ir_timer_t *t_codegen;
+extern ir_timer_t *t_sched;
+extern ir_timer_t *t_constr;
+extern ir_timer_t *t_finish;
+extern ir_timer_t *t_emit;
+extern ir_timer_t *t_other;
+extern ir_timer_t *t_execfreq;
+extern ir_timer_t *t_verify;
+extern ir_timer_t *t_heights;
+extern ir_timer_t *t_live; /**< timer for liveness calculation */
+extern ir_timer_t *t_ssa_constr; /**< timer for ssa reconstruction */
+extern ir_timer_t *t_ra_prolog; /**< timer for prolog */
+extern ir_timer_t *t_ra_epilog; /**< timer for epilog */
+extern ir_timer_t *t_ra_constr; /**< timer for spill constraints */
+extern ir_timer_t *t_ra_spill; /**< timer for spilling */
+extern ir_timer_t *t_ra_spill_apply;
+extern ir_timer_t *t_ra_color; /**< timer for graph coloring */
+extern ir_timer_t *t_ra_ifg; /**< timer for building interference graph */
+extern ir_timer_t *t_ra_copymin; /**< timer for copy minimization */
+extern ir_timer_t *t_ra_ssa; /**< timer for ssa destruction */
+extern ir_timer_t *t_ra_other; /**< timer for remaining stuff */
+