+
+/**
+ * Returns the libFirm configuration parameter for this backend.
+ */
+static const backend_params *arm_get_libfirm_params(void) {
+ static const ir_settings_if_conv_t ifconv = {
+ 4, /* maxdepth, doesn't matter for Psi-conversion */
+ arm_is_psi_allowed /* allows or disallows Psi creation for given selector */
+ };
+ static ir_settings_arch_dep_t ad = {
+ 1, /* allow subs */
+ 1, /* Muls are fast enough on ARM but ... */
+ 31, /* ... one shift would be possible better */
+ 0, /* SMUL is needed, only in Arch M */
+ 0, /* UMUL is needed, only in Arch M */
+ 32, /* SMUL & UMUL available for 32 bit */
+ };
+ static backend_params p = {
+ 1, /* need dword lowering */
+ 0, /* don't support inline assembler yet */
+ NULL, /* no additional opcodes */
+ NULL, /* will be set later */
+ NULL, /* but yet no creator function */
+ NULL, /* context for create_intrinsic_fkt */
+ NULL, /* will be set below */
+ };
+
+ p.dep_param = &ad;
+ p.if_conv_info = &ifconv;
+ return &p;
+}
+
+/* fpu set architectures. */
+static const lc_opt_enum_int_items_t arm_fpu_items[] = {
+ { "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
+ { "fpe", ARM_FPU_ARCH_FPE },
+ { "fpa", ARM_FPU_ARCH_FPA },
+ { "vfp1xd", ARM_FPU_ARCH_VFP_V1xD },
+ { "vfp1", ARM_FPU_ARCH_VFP_V1 },
+ { "vfp2", ARM_FPU_ARCH_VFP_V2 },
+ { NULL, 0 }
+};
+
+static lc_opt_enum_int_var_t arch_fpu_var = {
+ &arm_isa_template.fpu_arch, arm_fpu_items
+};
+
+static const lc_opt_table_entry_t arm_options[] = {
+ LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
+ LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names),
+ LC_OPT_LAST
+};