- "gp" => [
- { "name" => "r0", "type" => 1 },
- { "name" => "r1", "type" => 1 },
- { "name" => "r2", "type" => 1 },
- { "name" => "r3", "type" => 1 },
- { "name" => "r4", "type" => 2 },
- { "name" => "r5", "type" => 2 },
- { "name" => "r6", "type" => 2 },
- { "name" => "r7", "type" => 2 },
- { "name" => "r8", "type" => 2 },
- { "name" => "r9", "type" => 2 },
- { "name" => "r10", "type" => 2 },
- { "name" => "r11", "type" => 2 },
- { "name" => "r12", "type" => 6 }, # reserved for linker
- { "name" => "sp", "type" => 6 }, # this is our stack pointer
- { "name" => "lr", "type" => 3 }, # this is our return address
- { "name" => "pc", "type" => 6 }, # this is our program counter
- { "name" => "rxx", "type" => 6 }, # dummy register for no_mem
- { "mode" => "mode_Iu" }
- ],
- "fp" => [
- { "name" => "f0", "type" => 1 },
- { "name" => "f1", "type" => 1 },
- { "name" => "f2", "type" => 1 },
- { "name" => "f3", "type" => 1 },
- { "name" => "f4", "type" => 2 },
- { "name" => "f5", "type" => 2 },
- { "name" => "f6", "type" => 2 },
- { "name" => "f7", "type" => 2 },
- { "name" => "fxx", "type" => 6 }, # dummy register for no_mem
- { "mode" => "mode_D" }
- ]
-); # %reg_classes
-
-#--------------------------------------------------#
-# _ #
-# (_) #
-# _ __ _____ __ _ _ __ ___ _ __ ___ #
-# | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
-# | | | | __/\ V V / | | | | (_) | |_) \__ \ #
-# |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
-# | | #
-# |_| #
-#--------------------------------------------------#
-
-%nodes = (
-
-#-----------------------------------------------------------------#
-# _ _ _ #
-# (_) | | | | #
-# _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
-# | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
-# | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
-# |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
-# __/ | #
-# |___/ #
-#-----------------------------------------------------------------#
-
-# commutative operations
-
-"Add" => {
- "op_flags" => "C",
- "irn_flags" => "R",
- "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. ADD %D1, %S1, %S2%X0 /* Add(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Add_i" => {
- "irn_flags" => "R",
- "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "cmp_attr" => 'return attr_a->value != attr_b->value;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. ADD %D1, %S1, %C /* Add(%C, %S1) -> %D1, (%A1, const) */'
-},
-
-"Mul" => {
- #"op_flags" => "C",
- "irn_flags" => "R",
- "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "!in_r1" ] },
- "emit" =>'. MUL %D1, %S1, %S2 /* Mul(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Mla" => {
- #"op_flags" => "C",
- "irn_flags" => "R",
- "comment" => "construct Mla: Mla(a, b, c) = a * b + c",
- "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in_r1" ] },
- "emit" =>'. MLA %D1, %S1, %S2, %S3 /* Mla(%S1, %S2, %S3) -> %D1, (%A1, %A2, %A3) */'
-},
-
-"And" => {
- "op_flags" => "C",
- "irn_flags" => "R",
- "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. AND %D1, %S1, %S2%X0 /* And(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"And_i" => {
- "irn_flags" => "R",
- "comment" => "construct And: And(a, const) = And(const, a) = a AND const",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. AND %D1, %S1, %C /* And(%C, %S1) -> %D1, (%A1, const) */',
- "cmp_attr" => 'return attr_a->value != attr_b->value;'
-},
-
-"Or" => {
- "op_flags" => "C",
- "irn_flags" => "R",
- "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. ORR %D1, %S1, %S2%X0 /* Or(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Or_i" => {
- "irn_flags" => "R",
- "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "cmp_attr" => 'return attr_a->value != attr_b->value;',
- "emit" => '. ORR %D1, %S1, %C /* Or(%C, %S1) -> %D1, (%A1, const) */'
-},
-
-"Eor" => {
- "op_flags" => "C",
- "irn_flags" => "R",
- "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. EOR %D1, %S1, %S2%X0 /* Xor(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Eor_i" => {
- "irn_flags" => "R",
- "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "cmp_attr" => 'return attr_a->value != attr_b->value;',
- "emit" => '. EOR %D1, %S1, %C /* Xor(%C, %S1) -> %D1, (%A1, const) */'
-},
-
-# not commutative operations
-
-"Bic" => {
- "irn_flags" => "R",
- "comment" => "construct Bic: Bic(a, b) = a AND ~b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. BIC %D1, %S1, %S2%X0 /* AndNot(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Bic_i" => {
- "irn_flags" => "R",
- "comment" => "construct Bic: Bic(a, const) = a AND ~const",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. BIC %D1, %S1, %C /* AndNot(%C, %S1) -> %D1, (%A1, const) */',
- "cmp_attr" => 'return attr_a->value != attr_b->value;'
-},
-
-"Sub" => {
- "irn_flags" => "R",
- "comment" => "construct Sub: Sub(a, b) = a - b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. SUB %D1, %S1, %S2%X0 /* Sub(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Sub_i" => {
- "irn_flags" => "R",
- "comment" => "construct Sub: Sub(a, const) = a - const",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "cmp_attr" => 'return attr_a->value != attr_b->value;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. SUB %D1, %S1, %C /* Sub(%S1, %C) -> %D1, (%A1, const) */',
-},
-
-"Rsb" => {
- "irn_flags" => "R",
- "comment" => "construct Rsb: Rsb(a, b) = b - a",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. RSB %D1, %S1, %S2%X0 /* Rsb(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Rsb_i" => {
- "irn_flags" => "R",
- "comment" => "construct Rsb: Rsb(a, const) = const - a",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. RSB %D1, %S1, %C /* Rsb(%S1, %C) -> %D1, (%A1, const) */',
- "cmp_attr" => 'return attr_a->value != attr_b->value;'
-},
-
-"Shl" => {
- "irn_flags" => "R",
- "comment" => "construct Shl: Shl(a, b) = a << b",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
- "emit" => '. MOV %D1, %S1, LSL %S2\t/* Shl(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Shr" => {
- "irn_flags" => "R",
- "comment" => "construct Shr: Shr(a, b) = a >> b",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
- "emit" => '. MOV %D1, %S1, LSR %S2 /* Shr(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Shrs" => {
- "irn_flags" => "R",
- "comment" => "construct Shrs: Shrs(a, b) = a >> b",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
- "emit" => '. MOV %D1, %S1, ASR %S2\t\t /* Shrs(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-#"RotR" => {
-# "irn_flags" => "R",
-# "comment" => "construct RotR: RotR(a, b) = a ROTR b",
-# "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
-# "emit" => '. MOV %D1, %S1, ROR %S2 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
-## "emit" => '. ror %S1, %S2, %D1 /* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
-#},
-
-#"RotL" => {
-# "irn_flags" => "R",
-# "comment" => "construct RotL: RotL(a, b) = a ROTL b",
-# "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
-# "emit" => '. rol %S1, %S2, %D1 /* RotL(%S1, %S2) -> %D1, (%A1, %A2) */'
-#},
-
-#"RotL_i" => {
-# "irn_flags" => "R",
-# "comment" => "construct RotL: RotL(a, const) = a ROTL const",
-# "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-# "emit" => '. rol %S1, %C, %D1 /* RotL(%S1, %C) -> %D1, (%A1, const) */'
-#},
-
-"Mov" => {
- "irn_flags" => "R",
- "comment" => "construct Mov: a = b",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. MOV %D1, %S1%X0\t/* Mov(%S1%X0) -> %D1, (%A1) */'
-},
-
-"Mov_i" => {
- "irn_flags" => "R",
- "comment" => "represents an integer constant",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "reg_req" => { "out" => [ "gp" ] },
- "emit" => '. MOV %D1, %C /* Mov Const into register */',
- "cmp_attr" => 'return attr_a->value != attr_b->value;'
-},
-
-"Mvn" => {
- "irn_flags" => "R",
- "comment" => "construct Not: Not(a) = !a",
- "attr" => "arm_shift_modifier mod, tarval *shf",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, mod); attr->value = shf;',
- "cmp_attr" => 'return (attr_a->instr_fl != attr_b->instr_fl) || (attr_a->value != attr_b->value);',
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" => '. MVN %D1, %S1%X0 /* ~(%S1%X0) -> %D1, (%A1) */'
-},
-
-"Mvn_i" => {
- "irn_flags" => "R",
- "comment" => "represents a negated integer constant",
- "attr" => "tarval *tv",
- "init_attr" => 'ARM_SET_SHF_MOD(attr, ARM_SHF_IMM); attr->value = tv;',
- "cmp_attr" => 'return attr_a->value != attr_b->value;',
- "reg_req" => { "out" => [ "gp" ] },
- "emit" => '. MVN %D1, %C /* Mov ~Const into register */',
-},
-
-"Abs" => {
- "irn_flags" => "R",
- "comment" => "construct Abs: Abs(a) = |a|",
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
- "emit" =>
-'. MOVS %S1, %S1, #0 /* set condition flag */\n
-. RSBMI %D1, %S1, #0 /* Neg(%S1) -> %D1, (%A1) */'
-},
-
-# other operations
-
-"EmptyReg" => {
- "op_flags" => "c",
- "irn_flags" => "R",
- "comment" => "just to get an empty register for calculations",
- "reg_req" => { "out" => [ "gp" ] },
- "emit" => '. /* %D1 now available for calculations */',
- "cmp_attr" => 'return 1;'
-},
-
-"Copy" => {
- "comment" => "implements a register copy",
- "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] },
-},
-
-"CopyB" => {
- "op_flags" => "F|H",
- "state" => "pinned",
- "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
- "reg_req" => { "in" => [ "!sp", "!sp", "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
-},
-
-"SymConst" => {
- "op_flags" => "c",
- "irn_flags" => "R",
- "comment" => "represents a symbolic constant",
- "attr" => "const char *label",
- "init_attr" => ' attr->symconst_label = label;',
- "reg_req" => { "out" => [ "gp" ] },
-# "emit" => '. LDR %D1, %C /* Mov Const into register */',
- "cmp_attr" =>
-' /* should be identical but ...*/
- return strcmp(attr_a->symconst_label, attr_b->symconst_label);'
-},
-
-"CondJmp" => {
- "op_flags" => "L|X|Y",
- "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
- "cmp_attr" => " return arm_comp_condJmp(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "none", "none"] },
-},
-
-"SwitchJmp" => {
- "op_flags" => "L|X|Y",
- "comment" => "construct switch",
- "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
- "cmp_attr" => " return 0;\n",
-},
-
-# Load / Store
-
-"Load" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. LDR %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
-# "emit" => '. LDR %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
-},
-
-"Loadb" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. LDRB %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
-# "emit" => '. LDRB %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
-},
-
-"Loadbs" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. LDRSB %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
-# "emit" => '. LDRSB %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
-},
-
-"Loadh" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. LDRH %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
-# "emit" => '. LDRH %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
-},
-
-"Loadhs" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "gp" ] },
- "emit" => '. LDRSH %D1, [%S1, #0] /* Load((%S1)) -> %D1, (%A1) */'
-# "emit" => '. LDRSH %D1, %S1, %O /* Load((%S1)) -> %D1, (%A1) */'
-},
-
-"Storeb" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. STRB %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
-# "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
-},
-
-"Storebs" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. STRSB %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
-# "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
-},
-
-"Storeh" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. STRH %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
-# "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
-},
-
-"Storehs" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. STRSH%S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
-# "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
-},
-
-"Store" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "gp", "gp", "none" ] },
- "emit" => '. STR %S2, [%S1, #0] /* Store(%S2) -> (%S1), (%A1, %A2) */'
-# "emit" => '. movl %S2, %O(%S1) /* Store(%S2) -> (%S1), (%A1, %A2) */'
-},
-
-"StoreStackM4Inc" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "sp", "gp", "gp", "gp", "gp", "none" ], "out" => [ "gp", "none" ] },
- "emit" => '. STMFD %S1!, {%S2, %S3, %S4, %S5} /* Store multiple on Stack*/'
-},
-
-"LoadStackM3" => {
- "op_flags" => "L|F",
- "irn_flags" => "R",
- "state" => "exc_pinned",
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "sp", "none" ], "out" => [ "gp", "gp", "gp", "none" ] },
- "emit" => '. LDMFD %S1, {%D1, %D2, %D3} /* Load multiple from Stack */'
-},
-
+ gp => [
+ { name => "r0", dwarf => 0 },
+ { name => "r1", dwarf => 1 },
+ { name => "r2", dwarf => 2 },
+ { name => "r3", dwarf => 3 },
+ { name => "r4", dwarf => 4 },
+ { name => "r5", dwarf => 5 },
+ { name => "r6", dwarf => 6 },
+ { name => "r7", dwarf => 7 },
+ { name => "r8", dwarf => 8 },
+ { name => "r9", dwarf => 9 },
+ { name => "r10", dwarf => 10 },
+ { name => "r11", dwarf => 11 },
+ { name => "r12", dwarf => 12 },
+ { name => "sp", dwarf => 13 },
+ { name => "lr", dwarf => 14 },
+ { name => "pc", dwarf => 15 },
+ { mode => $mode_gp }
+ ],
+ fpa => [
+ { name => "f0", dwarf => 96 },
+ { name => "f1", dwarf => 97 },
+ { name => "f2", dwarf => 98 },
+ { name => "f3", dwarf => 99 },
+ { name => "f4", dwarf => 100 },
+ { name => "f5", dwarf => 101 },
+ { name => "f6", dwarf => 102 },
+ { name => "f7", dwarf => 103 },
+ { mode => $mode_fp }
+ ],
+ flags => [
+ { name => "fl" },
+ { mode => $mode_flags, flags => "manual_ra" }
+ ],
+);
+
+$default_attr_type = "arm_attr_t";
+$default_copy_attr = "arm_copy_attr";
+
+%init_attr = (
+ arm_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
+ arm_SymConst_attr_t =>
+ "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
+ "\tinit_arm_SymConst_attributes(res, entity, symconst_offset);",
+ arm_CondJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
+ arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
+ arm_fConst_attr_t => "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);",
+ arm_load_store_attr_t =>
+ "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
+ "\tinit_arm_load_store_attributes(res, ls_mode, entity, entity_sign, offset, is_frame_entity);",
+ arm_shifter_operand_t =>
+ "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n",
+ arm_cmp_attr_t =>
+ "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n",
+ arm_farith_attr_t =>
+ "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
+ "\tinit_arm_farith_attributes(res, op_mode);",
+ arm_CopyB_attr_t =>
+ "\tinit_arm_attributes(res, irn_flags_, in_reqs, n_res);\n".
+ "\tinit_arm_CopyB_attributes(res, size);",
+);
+
+%compare_attr = (
+ arm_attr_t => "cmp_attr_arm",
+ arm_SymConst_attr_t => "cmp_attr_arm_SymConst",
+ arm_CondJmp_attr_t => "cmp_attr_arm_CondJmp",
+ arm_SwitchJmp_attr_t => "cmp_attr_arm_SwitchJmp",
+ arm_fConst_attr_t => "cmp_attr_arm_fConst",
+ arm_load_store_attr_t => "cmp_attr_arm_load_store",
+ arm_shifter_operand_t => "cmp_attr_arm_shifter_operand",
+ arm_CopyB_attr_t => "cmp_attr_arm_CopyB",
+ arm_cmp_attr_t => "cmp_attr_arm_cmp",
+ arm_farith_attr_t => "cmp_attr_arm_farith",
+);
+
+my %unop_shifter_operand_constructors = (
+ imm => {
+ attr => "unsigned char immediate_value, unsigned char immediate_rot",
+ custominit => "init_arm_shifter_operand(res, immediate_value, ARM_SHF_IMM, immediate_rot);",
+ reg_req => { in => [], out => [ "gp" ] },
+ },
+ reg => {
+ custominit => "init_arm_shifter_operand(res, 0, ARM_SHF_REG, 0);",
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ },
+ reg_shift_reg => {
+ attr => "arm_shift_modifier_t shift_modifier",
+ custominit => "init_arm_shifter_operand(res, 0, shift_modifier, 0);",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ },
+ reg_shift_imm => {
+ attr => "arm_shift_modifier_t shift_modifier, unsigned shift_immediate",
+ custominit => "init_arm_shifter_operand(res, 0, shift_modifier, shift_immediate);",
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ },
+);
+
+my %binop_shifter_operand_constructors = (
+ imm => {
+ attr => "unsigned char immediate_value, unsigned char immediate_rot",
+ custominit => "init_arm_shifter_operand(res, immediate_value, ARM_SHF_IMM, immediate_rot);",
+ reg_req => { in => [ "gp" ], out => [ "gp" ] },
+ ins => [ "left" ],
+ },
+ reg => {
+ custominit => "init_arm_shifter_operand(res, 0, ARM_SHF_REG, 0);",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ ins => [ "left", "right" ],
+ },
+ reg_shift_reg => {
+ attr => "arm_shift_modifier_t shift_modifier",
+ custominit => "init_arm_shifter_operand(res, 0, shift_modifier, 0);",
+ reg_req => { in => [ "gp", "gp", "gp" ], out => [ "gp" ] },
+ ins => [ "left", "right", "shift" ],
+ },
+ reg_shift_imm => {
+ attr => "arm_shift_modifier_t shift_modifier, unsigned shift_immediate",
+ custominit => "init_arm_shifter_operand(res, 0, shift_modifier, shift_immediate);",
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ ins => [ "left", "right" ],
+ },
+);
+
+my %cmp_shifter_operand_constructors = (
+ imm => {
+ attr => "unsigned char immediate_value, unsigned char immediate_rot, bool ins_permuted, bool is_unsigned",
+ custominit =>
+ "init_arm_shifter_operand(res, immediate_value, ARM_SHF_IMM, immediate_rot);\n".
+ "\tinit_arm_cmp_attr(res, ins_permuted, is_unsigned);",
+ reg_req => { in => [ "gp" ], out => [ "flags" ] },
+ ins => [ "left" ],
+ },
+ reg => {
+ attr => "bool ins_permuted, bool is_unsigned",
+ custominit =>
+ "init_arm_shifter_operand(res, 0, ARM_SHF_REG, 0);\n".
+ "\tinit_arm_cmp_attr(res, ins_permuted, is_unsigned);",
+ reg_req => { in => [ "gp", "gp" ], out => [ "flags" ] },
+ ins => [ "left", "right" ],
+ },
+ reg_shift_reg => {
+ attr => "arm_shift_modifier_t shift_modifier, bool ins_permuted, bool is_unsigned",
+ custominit =>
+ "init_arm_shifter_operand(res, 0, shift_modifier, 0);\n".
+ "\tinit_arm_cmp_attr(res, ins_permuted, is_unsigned);",
+ reg_req => { in => [ "gp", "gp", "gp" ], out => [ "flags" ] },
+ ins => [ "left", "right", "shift" ],
+ },
+ reg_shift_imm => {
+ attr => "arm_shift_modifier_t shift_modifier, unsigned shift_immediate, bool ins_permuted, bool is_unsigned",
+ custominit =>
+ "init_arm_shifter_operand(res, 0, shift_modifier, shift_immediate);\n".
+ "\tinit_arm_cmp_attr(res, ins_permuted, is_unsigned);",
+ reg_req => { in => [ "gp", "gp" ], out => [ "flags" ] },
+ ins => [ "left", "right" ],
+ },
+);